Obviousness

Obviousness Analysis of US Patent 9201834 under 35 U.S.C. § 103

This analysis of US Patent 9201834 proceeds under 35 U.S.C. § 103, which dictates that a patent claim is unpatentable if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). The effective priority date for US9201834 is October 11, 2011.

The provided patent text, specifically the "Description of the Prior Art" section, outlines the general state of the art at the time of the invention. However, it does not explicitly name or cite specific prior art patents or publications as required for a traditional obviousness analysis with specific references. Therefore, this analysis will be based on the general understanding of the prior art and common knowledge of a PHOSITA in the field of memory chip modules and electronic devices, as implied by the problems the patent aims to solve.

General Prior Art as Described in US9201834

The patent identifies the following shortcomings in the prior art:

1. Standardized, inflexible memory modules: Memories were typically designed as standard modules (e.g., JEDEC-compliant) that were independent from logic units, leading to fixed bus widths, signal levels, and operating frequencies. This resulted in "lower manufacturability, less flexibility and higher system migration cost among different process technology generations and different applications."
2. Integration challenges for memory and logic units: Integrating memories (often using advanced semiconductor processes) with logic units (using different processes) led to "poorer heat dissipation, higher power consumption and bad noise interference."

A PHOSITA in 2011, working in the field of semiconductor device packaging and memory system design, would have possessed knowledge of memory architectures, bus interfaces, power management techniques, thermal management solutions, and electromagnetic interference (EMI) shielding principles.

Obviousness of Independent Claim 1

Claim 1 describes a reconfigurable high-speed memory chip module comprising:

• A type of memory cell array group with multiple memory cell array ICs.
• A first transmission bus (coupled to the memory group) having a first programmable transmitting or receiving data rate and signal swing.
• A second transmission bus (coupled to a logic unit) having a second programmable transmitting or receiving data rate and signal swing.
• A logic unit (coupled to the first bus) for accessing the memory group and converting a first set of parallel data from the first bus into a second set of parallel data for the second bus.

Combination of Prior Art Elements and Motivation:

A PHOSITA would have been motivated to combine known elements to achieve the claimed reconfigurable memory module, driven by the desire to overcome the inflexibility and integration challenges described in the prior art.

1. Programmable Data Rate and Signal Swing (First and Second Transmission Buses):

   • Prior Art Problem: The patent explicitly states that prior art JEDEC standards dictated fixed bus widths, signal levels, and data rates, leading to "less flexibility and higher system migration cost."
   • Motivation: To address the lack of flexibility and high migration costs, a PHOSITA would have been motivated to introduce programmability into the memory interface parameters. Techniques for dynamic voltage and frequency scaling were well-known in processor and system-on-chip (SoC) design by 2011 for optimizing power consumption and performance. Applying similar programmability to memory bus interfaces, including data rates and signal swings, would have been an obvious design choice to allow a memory module to adapt to various logic units and application requirements, thereby enhancing flexibility and reducing migration costs. The patent itself notes that programmability allows for "higher performance, lower operating power, lower standby power, longer battery life or another functional enhancement," indicating these were desired outcomes in the prior art.

2. Logic Unit as a Data Converter and Bus Bridge:

   • Prior Art Knowledge: The concept of a dedicated logic unit (e.g., a memory controller or an interface bridge) to manage memory access and adapt data formats between different bus architectures was standard practice. For instance, converting between wider internal memory buses and narrower external system buses (parallel-to-parallel or parallel-to-serial conversion) was a common function of memory controllers in various computing systems.
   • Motivation: Given the need for flexibility between the internal memory array group and an external processor, a PHOSITA would naturally employ a logic unit to serve as an intermediary. This logic unit would enable the adaptation of data (e.g., converting a wider internal parallel data set to a potentially narrower external parallel data set, as described in the patent) to optimize communication with different system processors (ASICs or SOCs) while maintaining high-speed access to the memory arrays.

3. Two Transmission Buses with Different Characteristics:

   • Prior Art Knowledge: System architects commonly employed different bus structures and protocols for internal chip-to-chip communication within a module and external module-to-system communication. It was well-understood that an internal bus could be optimized for high bandwidth and low latency memory access, while an external bus could be designed for compatibility with a system processor interface.
   • Motivation: The motivation would be to optimize performance and power efficiency. The patent explains that "system power efficiency can be higher if bit width of the first transmission bus is wider and with smaller signal swing comparing to the second transmission bus." Conversely, "the system data transmission bandwidth and noise level can be best optimized for another application environments or conditions if the second transmission bus is wider and with smaller signal swing comparing to the first transmission bus." These statements indicate that the trade-offs and benefits of such an architecture were known and desired in the prior art.

Therefore, a PHOSITA, motivated by the known desire for more flexible, efficient, and adaptable memory solutions to overcome the limitations of rigid standards and complex integration, would have found it obvious to combine the well-known principles of programmable interfaces, bus bridging logic, and differentiated bus architectures to arrive at the subject matter of Claim 1.

Obviousness of Independent Claim 5

Claim 5 depends on Claim 1 and further specifies:

• "...wherein at least one through silicon via (TSV) exists within a non-active circuit region surrounding or partially surrounding an active circuit region of each of the memory cell array ICs."

Combination of Prior Art Elements and Motivation:

A PHOSITA would have been motivated to incorporate TSVs in the described manner, driven by the need to address the "poorer heat dissipation, higher power consumption and bad noise interference" problems in integrated memory and logic systems, as highlighted in the patent's own description of prior art.

1. Use of TSVs for EMI Shielding and Heat Dissipation:

   • Prior Art Problem: The prior art suffered from "bad noise interference" and "poorer heat dissipation" in integrated memory/logic systems.
   • Prior Art Knowledge: Through-Silicon Vias (TSVs) were a known technology for vertical interconnections in 3D integrated circuits by 2011. The concept of using conductive structures (like metal fences formed by TSVs or other means) for EMI shielding and as paths for heat dissipation was well-established in semiconductor packaging and electromagnetic theory. The patent itself notes that the benefits of using TSVs to form a metal fence for "better EMI shielding effect, better heat dissipation capability, and an better external noise isolation function" are "based on the magnetic-electronic theory available today." This acknowledges the underlying principles were already understood.
   • Motivation: A PHOSITA, actively seeking to mitigate noise and improve thermal performance in stacked or integrated ICs, would naturally consider deploying TSVs for these purposes.

2. Placement of TSVs within Non-Active Circuit Regions:

   • Prior Art Knowledge: It was a common design practice in integrated circuit layout to place power/ground routing, decoupling capacitors, and other non-active structures in peripheral or "non-active" areas of a chip to minimize interference with sensitive active circuitry and to optimize the utilization of the more valuable active circuit area.
   • Motivation: Combining the known benefits of TSVs for shielding/thermal management with the established practice of utilizing non-active regions for such structures would be an obvious design choice. The patent itself explains that using TSVs in non-active regions "can save power or ground supply line area within an active circuit region... to improving the manufacturing yield and cost," and improve dicing yield. These benefits reflect known design goals in the prior art.

3. Arrangement of TSVs to Surround or Partially Surround Active Regions:

   • Prior Art Knowledge: The principle of creating a "Faraday cage" or similar shielding structures by surrounding a sensitive area with conductive material was a fundamental concept in electrical engineering.
   • Motivation: To effectively shield an active circuit region from external noise or to channel heat away, a PHOSITA would predictably arrange conductive elements, such as TSVs connected to power or ground, to surround or partially surround the active region. This forms a "metal fence" as described in the patent, which is a direct application of known shielding principles to the problem of "bad noise interference."

Therefore, a PHOSITA, motivated to solve the acknowledged problems of heat, power, and noise in integrated memory and logic components, and conversant with TSV technology and fundamental IC design principles regarding shielding and thermal management, would have found it obvious to integrate TSVs into the non-active regions of memory ICs within a module as described in Claim 5, to form a metal fence for EMI shielding and improved heat dissipation.