Prior art

The USPTO database search for patent number US9164942B2 confirms its existence. It was issued on October 20, 2015, from application number 13/649,131, filed on October 11, 2012. The first named inventor is Weng-Dah Ken, and the original assignee is Etron Technology, Inc.. The patent is currently active and is expected to expire on June 27, 2034.

Here's an analysis of the most relevant prior art cited against US9164942B2, along with potential anticipation under 35 U.S.C. § 102. The analysis focuses on patents explicitly listed as "Citations" or "Patent Citations" in the provided text.

Most Relevant Prior Art for US9164942B2:

1. US6317377B1

• Full Citation: US6317377B1, "Semiconductor memory device"
• Publication/Filing Date: Filed April 12, 1999; Published/Issued November 13, 2001.
• Brief Description: This patent describes a semiconductor memory device.
• Potential Anticipation (35 U.S.C. § 102): Without more detailed information on the claims of US6317377B1, it is difficult to precisely determine which claims of US9164942B2 it anticipates. However, given its broad title "Semiconductor memory device," it could potentially anticipate fundamental aspects of a memory chip module, such as a memory cell array group (Claim 1) or individual memory cell array ICs.

2. US20040246801A1

• Full Citation: US20040246801A1, "Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation"
• Publication/Filing Date: Filed June 4, 2003; Published December 9, 2004.
• Brief Description: This application describes integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation.
• Potential Anticipation (35 U.S.C. § 102): This reference might anticipate aspects related to data transmission rates and modes of operation. Specifically, claims like Claim 9 or Claim 10 of US9164942B2, which discuss different transmitting and receiving data rates for the first and second transmission buses, could be potentially anticipated.

3. US20040260864A1

• Full Citation: US20040260864A1, "Reconfigurable memory module and method"
• Publication/Filing Date: Filed June 19, 2003; Published December 23, 2004.
• Brief Description: This patent describes a reconfigurable memory module and method.
• Potential Anticipation (35 U.S.C. § 102): The concept of a "reconfigurable memory module" could potentially anticipate aspects of US9164942B2 related to the memory cell array group and its interaction with the logic unit. This could potentially anticipate elements of Claim 1 related to the memory cell array group, and potentially claims related to data handling if "reconfigurable" implies different data paths or widths.

4. US7013359B1

• Full Citation: US7013359B1, "High speed memory interface system and method"
• Publication/Filing Date: Filed December 21, 2001; Published/Issued March 14, 2006.
• Brief Description: This patent describes a high speed memory interface system and method.
• Potential Anticipation (35 U.S.C. § 102): The title "High speed memory interface system and method" directly suggests anticipation of the core functionality of US9164942B2. This reference could potentially anticipate Claim 1 (high speed memory chip module), and specifically aspects of the first and second transmission buses, their widths, and data transfer (Claim 1, Claim 5).

5. US20070005831A1

• Full Citation: US20070005831A1, "Semiconductor memory system"
• Publication/Filing Date: Filed June 30, 2005; Published January 4, 2007.
• Brief Description: This patent describes a semiconductor memory system.
• Potential Anticipation (35 U.S.C. § 102): Similar to US6317377B1, the general nature of a "semiconductor memory system" could potentially anticipate the overall structure of the high speed memory chip module (Claim 1) or the electronics system device (Claim 19).

6. US7206876B2

• Full Citation: US7206876B2, "Input/output interface of an integrated circuit device"
• Publication/Filing Date: Filed April 15, 2003; Published/Issued April 17, 2007.
• Brief Description: This patent describes an input/output interface of an integrated circuit device.
• Potential Anticipation (35 U.S.C. § 102): This reference could potentially anticipate aspects of the I/O data buses of the memory cell array ICs (Claim 1) and the transmission buses (Claim 1). The concept of an I/O interface is central to how the memory and logic units communicate.

7. US7245239B2

• Full Citation: US7245239B2, "Synchronous parallel/serial converter"
• Publication/Filing Date: Filed January 14, 2005; Published/Issued July 17, 2007.
• Brief Description: This patent describes a synchronous parallel/serial converter.
• Potential Anticipation (35 U.S.C. § 102): This patent directly addresses a "parallel-to-serial converter," which is a key component described in US9164942B2 (Claim 5). This would very strongly anticipate Claim 5 and potentially other claims that rely on this conversion functionality.

8. US7385281B2

• Full Citation: US7385281B2, "Semiconductor integrated circuit device"
• Publication/Filing Date: Filed December 25, 2003; Published/Issued June 10, 2008.
• Brief Description: This patent describes a semiconductor integrated circuit device.
• Potential Anticipation (35 U.S.C. § 102): This general patent on a "semiconductor integrated circuit device" could potentially anticipate the fundamental integrated circuit components described in US91649942B2, such as the memory cell array ICs or the logic unit (Claim 1).

9. US20090024790A1

• Full Citation: US20090024790A1, "Memory circuit system and method"
• Publication/Filing Date: Filed July 31, 2006; Published January 22, 2009.
• Brief Description: This patent describes a memory circuit system and method.
• Potential Anticipation (35 U.S.C. § 102): The title "Memory circuit system and method" suggests it could potentially anticipate the overall memory system described in US9164942B2, including the memory cell array group and its interaction with a logic unit (Claim 1).

10. US20090039492A1

• Full Citation: US20090039492A1, "Stacked memory device"
• Publication/Filing Date: Filed August 6, 2007; Published February 12, 2009.
• Brief Description: This patent describes a stacked memory device.
• Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant as US9164942B2 describes various stacked configurations (e.g., FIGS. 2, 3, 5, 6). Therefore, claims related to the stacking of memory cell array ICs and logic units (e.g., descriptions in the detailed description referring to stacking, and potentially how TSVs are used in a stacked context), could be anticipated by this reference.

11. US7546497B2

• Full Citation: US7546497B2, "Semiconductor memory device and data write and read method thereof"
• Publication/Filing Date: Filed May 24, 2005; Published/Issued June 9, 2009.
• Brief Description: This patent describes a semiconductor memory device and data write and read method thereof.
• Potential Anticipation (35 U.S.C. § 102): This reference could anticipate the fundamental operation of accessing memory, including writing and reading data, which is a core function described in Claim 1 of US9164942B2 (logic unit accessing the memory cell array group).

12. US7680966B1

• Full Citation: US7680966B1, "Memory interface including generation of timing signals for memory operation"
• Publication/Filing Date: Filed June 29, 2004; Published/Issued March 16, 2010.
• Brief Description: This patent describes a memory interface including generation of timing signals for memory operation.
• Potential Anticipation (35 U.S.C. § 102): This patent directly relates to memory interfaces, a key aspect of US9164942B2 (first and second transmission buses). It could potentially anticipate the design and operation of these interfaces and the data transfer across them (Claim 1).

13. US20100235554A1

• Full Citation: US20100235554A1, "Reconfigurable point-to-point memory interface"
• Publication/Filing Date: Filed October 19, 2007; Published September 16, 2010.
• Brief Description: This patent describes a reconfigurable point-to-point memory interface.
• Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant due to its focus on a "reconfigurable point-to-point memory interface." This could potentially anticipate various aspects of the first and second transmission buses and their configuration (Claim 1, Claim 5), especially if the reconfigurability relates to bus width or data rates.

14. US7810017B2

• Full Citation: US7810017B2, "Variable sector-count ECC"
• Publication/Filing Date: Filed March 20, 2006; Published/Issued October 5, 2010.
• Brief Description: This patent describes a variable sector-count ECC.
• Potential Anticipation (35 U.S.C. § 102): While not directly about the physical bus structure, if US9164942B2's claims implicitly rely on certain data handling or error correction strategies that are standard in memory systems with variable data widths, then aspects of this patent could be relevant. However, without more explicit connections in US9164942B2's claims to ECC, direct anticipation is less likely for most claims.

15. US7903685B2

• Full Citation: US7903685B2, "System and method for reformatting data"
• Publication/Filing Date: Filed June 3, 2003; Published/Issued March 8, 2011.
• Brief Description: This patent describes a system and method for reformatting data.
• Potential Anticipation (35 U.S.C. § 102): This patent could potentially anticipate Claim 1 and Claim 5 of US9164942B2, specifically the logic unit's function of "converting the first set of parallel data of the first transmission bus into a second set of parallel data through a second transmission bus." Data reformatting is directly analogous to parallel-to-serial conversion and changing bit widths.

16. US8036052B2

• Full Citation: US8036052B2, "Semiconductor memory device and test method thereof"
• Publication/Filing Date: Filed February 22, 2007; Published/Issued October 11, 2011.
• Brief Description: This patent describes a semiconductor memory device and test method thereof.
• Potential Anticipation (35 U.S.C. § 102): Similar to other general memory device patents, this could potentially anticipate the fundamental structure of the memory cell array ICs (Claim 1). If any claims of US9164942B2 implicitly rely on specific testability features that are common in semiconductor memory devices, there might be a broader anticipation.

17. US8473653B2

• Full Citation: US8473653B2, "Semiconductor device, control method for the semiconductor device and information processing system including the same"
• Publication/Filing Date: Filed October 9, 2009; Published/Issued June 25, 2013.
• Brief Description: This patent describes a semiconductor device, control method for the semiconductor device and information processing system including the same.
• Potential Anticipation (35 U.S.C. § 102): This broad patent could potentially anticipate the overall electronics system device (Claim 19) or the high speed memory chip module (Claim 1) if it details similar integrated components and their control.

18. US8803545B2

• Full Citation: US8803545B2, "Semiconductor device semiconductor device testing method, and data processing system"
• Publication/Filing Date: Filed January 18, 2010; Published/Issued August 12, 2014.
• Brief Description: This patent describes a semiconductor device, semiconductor device testing method, and data processing system.
• Potential Anticipation (35 U.S.C. § 102): Similar to the previous broad patents, this could potentially anticipate the overall electronics system device (Claim 19) or the high speed memory chip module (Claim 1) if it covers similar integrated components and their functionality. The data processing aspect might also be relevant to the ASIC processor and its function (Claim 19).

Prior Art from "Family Cites Families" (Less direct, but worth noting):

While "Family Cites Families" usually indicates a broader field of art rather than direct anticipation, some of these references might contain elements relevant to US9164942B2. Without specific claim analysis for each, the potential for anticipation is less direct than the "Patent Citations" listed above.

• US5175841A: "Data processing device with multiple on-chip memory buses" (Filed March 13, 1987; Issued December 29, 1992). This could be relevant to the concept of multiple buses and varying bus widths (Claim 1).
• US5375083A: "Semiconductor integrated circuit including a substrate having a memory cell array surrounded by a well structure" (Filed February 4, 1993; Issued December 20, 1994). This could be relevant to the physical structure of memory cell arrays.
• JPH10134022A: "Semiconductor integrated circuit" (Filed October 31, 1996; Published May 22, 1998). General integrated circuit technology.
• US6009023A: "High performance DRAM structure employing multiple thickness gate oxide" (Filed May 26, 1998; Issued December 28, 1999). Could be relevant to the MOSFET process and gate lengths (Claim 1).
• EP1157419A1: "Non-volatile memory cells and periphery" (Filed December 21, 1999; Published November 28, 2001). Could be relevant to the memory cell array ICs, especially flash or NVM (Claim 2).
• DE10245037B4: "Method of designing DRAM semiconductor memory devices" (Filed September 26, 2002; Published August 23, 2007). Could be relevant to the DRAM IC (Claim 2).
• CN100336045C: "Multifunction chipset and related method" (Filed November 19, 2004; Published September 5, 2007). Could be broadly relevant to the system device (Claim 19) if it integrates memory and logic.
• US7390700B2: "Packaged system of semiconductor chips having a semiconductor interposer" (Filed April 7, 2006; Issued June 24, 2008). Highly relevant to the interposer embodiments (Claim 3, Claim 4, Claim 20, Claim 21).
• US7569918B2: "Semiconductor package-on-package system including integrated passive components" (Filed May 1, 2006; Issued August 4, 2009). Highly relevant to the Package-in-Package (PIP), Package on package (POP), or System in Package (SIP) configurations mentioned in the description, and potentially Claim 1's overall module.
• KR100867640B1: "System-on-Chip with Image Processing Memory with Multiple Access Paths" (Filed February 6, 2007; Published November 10, 2008). Could be relevant to the ASIC/SOC processor and memory access (Claim 5, Claim 19).
• CN101752351A: "Programmable array module" (Filed December 4, 2008; Published June 23, 2010). Could be broadly relevant to the memory cell array group (Claim 1) or the logic unit's functionality.