Obviousness

Obviousness Analysis of US Patent 9164942 under 35 U.S.C. § 103

This analysis assesses the obviousness of US Patent 9164942 (the '942 patent) based on the prior art references cited within the patent, in accordance with 35 U.S.C. § 103. The '942 patent aims to address challenges in integrating memory and logic units, specifically concerning power consumption, heat dissipation, noise interference, and manufacturing difficulty, by proposing a high-speed memory chip module with differentiated semiconductor processes and efficient data transmission.

Background of the Invention (as described in US9164942)

The '942 patent identifies several problems in the prior art concerning memory and logic integration:

• Memories are typically designed as standard modules, independent of specific logic units, rather than for predetermined logic units.
• Integrating discrete memories (often using more advanced semiconductor processes for density) with logic units (using different process generations) results in poorer heat dissipation, higher power consumption, bad noise interference, and manufacturing difficulties.

The independent claims (Claim 1 and Claim 19) of the '942 patent describe a high-speed memory chip module and an electronics system device incorporating such a module.

Obviousness of Claim 1: High Speed Memory Chip Module

Claim 1 Elements:

1. A high-speed memory chip module.
2. A type of memory cell array group comprising multiple memory cell array integrated circuits (ICs), each with an I/O data bus and at least one memory cell array.
3. Each memory cell array IC corresponds to a first MOSFET process with a first MOSFET gate length.
4. A logic unit for accessing the memory cell array group via a first transmission bus, transmitting a first set of parallel data.
5. The bus width of the first transmission bus is wider than the bus width of the I/O data bus of each memory cell array IC.
6. The logic unit corresponds to a second MOSFET process with a second MOSFET gate length.
7. The first MOSFET gate length is longer than the second MOSFET gate length (i.e., memory uses a larger/older process node than logic).
8. The logic unit converts the first set of parallel data from the first transmission bus into a second set of parallel data via a second transmission bus.

Combination of Prior Art References for Claim 1:
A combination of the following prior art references, along with the ordinary skill in the art, would render Claim 1 obvious:

1. US20090039492A1 ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)): "Stacked memory device"
2. US7245239B2 (Infineon Technologies Ag): "Synchronous parallel/serial converter"
3. US6009023A (Etron Technology, Inc.): "High performance DRAM structure employing multiple thickness gate oxide" and/or general knowledge of semiconductor process technology.

Explanation of Obviousness and Motivation:

A person having ordinary skill in the art (PHOSITA) in memory system design, faced with the problems of efficiently integrating memory and logic units with differing process technologies (as stated in the '942 patent's background), would have been motivated to combine the teachings of these references.

• Integrated Memory and Logic with Differentiated Process Technologies (Elements 2, 3, 4, 6, 7):

  • US20090039492A1 teaches a "stacked memory device". It would be obvious to a PHOSITA to implement a "type of memory cell array group" (Claim 1, element 2) using multiple memory ICs in a stacked configuration, as this was a known method for achieving high-density memory modules.
  • It was well-understood in the prior art (and acknowledged by the '942 patent itself) that memory ICs, particularly DRAMs, are typically fabricated using semiconductor processes optimized for density and cost, which often means larger feature sizes and thus "first MOSFET gate length" compared to the cutting-edge processes used for high-performance logic units [Description]. US6009023A illustrates the concept of employing "multiple thickness gate oxide" within a DRAM structure to optimize performance, demonstrating an awareness of tailoring process parameters for specific functions within semiconductor devices. A PHOSITA would routinely select a more mature process (resulting in a longer MOSFET gate length) for the memory cell array ICs (Claim 1, element 3) to maximize yield and minimize cost for the dense memory arrays, while selecting a more advanced process (resulting in a shorter MOSFET gate length) for the "logic unit" (Claim 1, elements 6, 7) to achieve higher speed and lower power consumption for logic operations. This pragmatic approach directly addresses the "manufacturing difficulty," "poorer heat dissipation," and "higher power consumption" issues by optimizing each component's manufacturing process for its specific role within the module.

• Efficient Data Transmission and Conversion (Elements 4, 5, 8):

  • US7245239B2 explicitly teaches a "synchronous parallel/serial converter". To handle the high bandwidth requirements of accessing a group of memory ICs within the module while maintaining a manageable external interface, a PHOSITA would be motivated to use a wider "first transmission bus" (Claim 1, element 5: "bus width... wider than bus width of an I/O data bus of each... memory cell array ICs") for internal data transfer between the memory group and the logic unit. The logic unit would then incorporate a parallel-to-serial converter (as taught by US7245239B2) to efficiently "convert the first set of parallel data... into a second set of parallel data through a second transmission bus" (Claim 1, element 8) for communication with other system components. This approach balances internal bandwidth with external interface constraints, reducing pin count and simplifying routing, thereby enhancing "higher data transmission efficiency" and contributing to "lower power consumption" by optimizing signal swings and bus widths as described in the '942 patent's summary [Summary of the Invention].

Therefore, a PHOSITA, aiming to integrate memory and logic effectively to overcome known system-level challenges, would have found it obvious to combine a stacked memory device, different semiconductor process technologies for memory and logic, and a parallel-to-serial converter to create a high-speed memory chip module as claimed in Claim 1.

Obviousness of Claim 19: Electronics System Device

Claim 19 Elements:
Claim 19 describes an electronics system device that includes the high-speed memory chip module of Claim 1, with the addition of:

1. An ASIC processor.
2. The logic unit transmits the second set of parallel data to the ASIC processor.
3. The ASIC processor executes a predetermined function corresponding to the second set of parallel data while under operating condition.
4. Bit width of the first set and the second set of parallel data are different.

Combination of Prior Art References for Claim 19:
The combination of references for Claim 1 (US20090039492A1, US7245239B2, US6009023A, and general knowledge of semiconductor processes), further combined with general knowledge of system architecture (e.g., evidenced by KR10086760B1 (Samsung Electronics Co., Ltd.): "System-on-Chip with Image Processing Memory with Multiple Access Paths" or CN100336045C (VIA Technologies, Inc.): "Multifunction chipset and related method"), would render Claim 19 obvious.

Explanation of Obviousness and Motivation:

• Integration with an ASIC Processor (Elements 1, 2, 3):

  • Once the high-speed memory chip module (as rendered obvious for Claim 1) is conceived, its integration into a larger electronic system is a natural next step. Prior art such as KR100867640B1 describes a "System-on-Chip with Image Processing Memory with Multiple Access Paths," demonstrating the conventional practice of coupling memory directly with a processor. Similarly, CN100336045C describes a "Multifunction chipset and related method," which inherently involves processors interacting with memory.
  • A PHOSITA designing an electronic system would routinely connect a memory module to an "ASIC processor" to enable the processor to access and process data ("executes a predetermined function corresponding to the second set of parallel data") [Claim 19]. The logic unit's function of transmitting data to the ASIC processor is a fundamental aspect of any memory subsystem serving a processor.

• Differing Bit Widths (Element 4):

  • The element stating that "bit width of the first set and the second set of parallel data are different" is directly addressed by the parallel-to-serial conversion taught by US7245239B2, which forms part of the obviousness argument for Claim 1. Such conversion inherently changes the bit width of the data stream.

Motivation for Combination:
The motivation for combining these elements is to create a functional electronic system that utilizes the benefits of the high-speed memory chip module. The very purpose of the memory module, as described in the '942 patent, is to provide efficient data access for a processor. The problems identified in the '942 patent's background (heat, power, noise, manufacturing difficulty) are system-level challenges that are addressed by the integrated memory module and its optimized interfaces, thereby motivating a PHOSITA to incorporate such a module into an ASIC-based system for improved performance and efficiency.