Patent 9092352
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
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Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
The provided patent text for US9092352 details its priority to US patent application Ser. No. 11/330,524, filed on January 11, 2006, which subsequently issued as US Pat. No. 7,562,285. This means the effective priority date for US9092352 is January 11, 2006. The "RELATED APPLICATIONS" and "References" sections within the Google Patents record for US9092352 primarily list continuation and divisional patents from the same patent family, all sharing this earliest priority date. These family members are not prior art for an obviousness analysis under 35 U.S.C. § 103 for US9092352 itself.
The "Prior art keywords" section on the Google Patents page (e.g., "error," "data," "detection information") offers general technical concepts but does not identify specific prior art documents external to the patent family. Therefore, the provided patent text does not contain specific external prior art references that predate the January 11, 2006 priority date and would be necessary for a robust obviousness analysis.
Without specific prior art references that predate the critical date, a comprehensive obviousness analysis as typically conducted under 35 U.S.C. § 103 cannot be performed. Such an analysis requires identifying specific prior art documents, detailing their disclosures, and explaining how a person having ordinary skill in the art (PHOSITA) would have been motivated to combine their teachings to arrive at the claimed invention with a reasonable expectation of success.
To proceed with an obviousness analysis, external prior art searches would be necessary to identify relevant patents or publications disclosing elements such as:
- Memory controllers with error detection and correction.
- Bidirectional data links coupled with unidirectional error code transfer (sideband or in-band).
- Dynamic generation and comparison of error-detection information at both a controller and a memory device.
- Retry mechanisms for data errors in memory communication.
- Error detection for write mask information and associated write disablement.
A PHOSITA in the field of memory systems and error detection/correction in early 2006 would have been generally aware of these concepts. However, identifying specific combinations of prior art that render the claims obvious requires concrete evidence from documents that existed before the January 11, 2006 priority date.
Given these limitations, I cannot identify combinations of prior art from the provided text that would render the claims of US9092352 obvious or explain the motivation to combine them, as no such external prior art references are supplied within the provided authoritative patent information.
Generated 5/25/2026, 6:46:04 PM