Prior art

To identify the most relevant prior art for US patent 8,370,543, I will focus on the "Citations" section of the patent provided by Google Patents, as these are the references considered by the examiner and often represent the closest prior art. I will then briefly describe each cited patent and identify which claims it might potentially anticipate. The USPTO's Patent Public Search tool is a primary resource for this type of analysis.

Here's an analysis of the patent citations listed for US8370543, focusing on potential anticipation under 35 U.S.C. § 102. Anticipation means that every element of a patent claim is found, either explicitly or inherently, in a single prior art reference.

Most Relevant Prior Art for US Patent 8,370,543

Based on the provided patent text, here are some of the cited prior art documents and an initial assessment of their relevance:

1. US6055607A (Interface queue with bypassing capability for main storage unit)

• Full Citation: US6055607A, Unisys Corporation, filed Dec. 23, 1996, granted Apr. 25, 2000.
• Brief Description: This patent describes an interface queue system for a main storage unit that includes bypassing capabilities. It appears to deal with managing data flow, potentially in different timing scenarios.
• Potential Anticipation (35 U.S.C. § 102): The general concept of managing requests and data flow, especially with queuing mechanisms, could potentially anticipate elements of Claim 1 (circuit), particularly the "load logic coupled to output the synchronized request signals according to a predetermined priority," and Claim 9 (method), specifically "outputting the captured states according to a predetermined priority." The aspect of "bypassing capability" might also be relevant to the priority logic.

2. US4965794A (Telecommunications FIFO)

• Full Citation: US4965794A, Dallas Semiconductor Corporation, filed Oct. 5, 1987, granted Oct. 23, 1990.
• Brief Description: This patent describes a First-In, First-Out (FIFO) memory specifically for telecommunications applications. FIFOs are commonly used for synchronizing data between different clock domains.
• Potential Anticipation (35 U.S.C. § 102): A telecommunications FIFO inherently addresses synchronization between data streams, which is central to US8370543. Elements of this patent could potentially anticipate aspects of Claim 1 (circuit) regarding "synchronizing logic configured to synchronize the stored request signals to a second time domain," and Claim 9 (method) concerning "synchronously clocking the captured states along separate logic paths." Given the context of asynchronous communication ports, a FIFO is highly relevant.

3. US5444853A (System and method for transferring data between a plurality of virtual FIFO's and a peripheral via a hardware FIFO and selectively updating control information associated with the virtual FIFO's)

• Full Citation: US5444853A, Seiko Epson Corporation, filed Mar. 31, 1992, granted Aug. 22, 1995.
• Brief Description: This patent describes a system using both virtual and hardware FIFOs for data transfer to a peripheral, including updating control information. This implies handling multiple data streams and synchronization.
• Potential Anticipation (35 U.S.C. § 102): The use of multiple FIFOs and the concept of "selectively updating control information" are highly relevant to managing resource access and busy states. This could potentially anticipate aspects of Claim 1 (circuit) (e.g., "first logic... configured to store selected of the request signals," "synchronizing logic," and "load logic") and Claim 9 (method) (e.g., "capturing a state of selected input signals responsive to a timing signal," "synchronously clocking the captured states," and "outputting the captured states according to a predetermined priority"). It also relates to Claim 16 (system) regarding the "logic unit coupled between the first and second devices configured to latch resource request signals... and synchronize latched resource request signals."

4. US5898893A (Fifo memory system and method for controlling)

• Full Citation: US5898893A, Xilinx, Inc., filed Oct. 10, 1995, granted Apr. 27, 1999.
• Brief Description: This patent describes a FIFO memory system and method for controlling it. As with other FIFO patents, its relevance stems from its function in synchronizing data.
• Potential Anticipation (35 U.S.C. § 102): Similar to US4965794A, this patent's focus on FIFO memory systems and control methods directly relates to the core synchronization and data handling aspects of US8370543. It could potentially anticipate the "synchronizing logic" of Claim 1, the "synchronously clocking" step of Claim 9, and the "logic unit" of Claim 16 that latches and synchronizes signals.

5. US6269413B1 (System with multiple dynamically-sized logical FIFOs sharing single memory and with read/write pointers independently selectable and simultaneously responsive to respective read/write FIFO selections)

• Full Citation: US6269413B1, Hewlett Packard Company, filed Oct. 30, 1998, granted Jul. 31, 2001.
• Brief Description: This patent describes a system with multiple logical FIFOs sharing a single memory, allowing for independent and simultaneous read/write pointer control. This is highly relevant to managing multiple resource requests.
• Potential Anticipation (35 U.S.C. § 102): The ability to manage multiple, independently controlled FIFOs within a single memory, with dynamic sizing and independent read/write pointers, directly addresses resource allocation and busy detection in a multi-port scenario. This patent could potentially anticipate aspects of Claim 1 (circuit) (e.g., "first logic coupled to receive request signals," "synchronizing logic," and "load logic for ensuring that only one port is reported as busy at a time coupled to the synchronization logic"), Claim 9 (method) (e.g., "capturing a state of selected input signals," "synchronously clocking the captured states," and "outputting the captured states according to a predetermined priority"), and Claim 16 (system) (e.g., "a second device having a plurality of different resources accessible by the first device," and a "logic unit coupled between the first and second devices configured to latch resource request signals... and synchronize latched resource request signals"). The "one hot port busy setting" mentioned in the description of US8370543 for load logic 308 seems particularly vulnerable to this type of prior art.

This list provides a starting point for a more in-depth prior art analysis. A full analysis would involve a detailed comparison of each element of the claims of US8370543 against the disclosures of these and other cited prior art documents.