Obviousness

Obviousness Analysis of US Patent 8,370,543 under 35 U.S.C. § 103

This analysis identifies combinations of prior art references that would render the claims of US patent 8,370,543 obvious to a person having ordinary skill in the art (POSA). The problem addressed by US8370543 is synchronizing device resource access information between independent time domains without imposing pulse width restrictions on control signals or requiring high-speed clocks, while also efficiently managing multiple resource requests and ensuring singular access.

The conventional designs discussed in US8370543 (FIGS. 1A and 1B) highlight the prior art's limitations: pulse width restrictions with slow clocks (FIG. 1A) or increased complexity and power with fast clocks (FIG. 1B). The claimed invention aims to overcome these by using a read/write strobe signal as a clock to capture requests and then synchronizing them to the core clock domain with load logic that prioritizes access.

Combinations of Prior Art for Obviousness

A POSA would be motivated to combine elements from various prior art references to achieve the functionality described in US8370543, particularly given the known challenges of clock domain crossing and resource arbitration in asynchronous systems.

Combination 1: US6269413B1 in view of US4965794A (or US5898893A) and US6055607A

This combination addresses the core aspects of all independent claims (Claims 1, 9, and 16).

• US6269413B1 (System with multiple dynamically-sized logical FIFOs sharing single memory and with read/write pointers independently selectable and simultaneously responsive to respective read/write FIFO selections) provides a robust foundation for managing multiple resource requests and their states.

  • Basis for "first logic" / "capturing selected input signals" / "logic unit to latch resource request signals": This patent describes a system where "multiple dynamically-sized logical FIFOs" receive data, and their "read/write pointers [are] independently selectable and simultaneously responsive to respective read/write FIFO selections." This directly teaches a mechanism to receive and "capture" (latch/store) selected input signals (resource requests) via logical FIFOs in response to timing signals (read/write FIFO selections). The logical FIFOs effectively act as the "first logic" for storing selected request signals.
  • Basis for "outputting according to a predetermined priority" / "load logic": The "independently selectable and simultaneously responsive" nature of the read/write pointers in a system with "multiple logical FIFOs sharing single memory" implies a need for arbitration to manage access to the shared resource. A POSA would find it obvious to implement a priority scheme (e.g., a "one-hot" setting as described for load logic 308 in US8370543) for outputting these captured states (resource requests) to prevent conflicts and ensure orderly access, especially when a resource can only serve one request at a time. This would function as the "load logic."

• US4965794A (Telecommunications FIFO) or US5898893A (Fifo memory system and method for controlling) provide explicit teachings on synchronization between different clock domains.

  • Basis for "synchronizing logic" / "synchronously clocking" / "synchronize latched resource request signals to the first clock domain": FIFOs are a standard and well-known solution for reliably transferring data and control signals between asynchronous clock domains. US4965794A explicitly describes a FIFO for telecommunications, inherently dealing with such synchronization, and US5898893A details a FIFO memory system and its control. A POSA, faced with the need to synchronize latched resource requests from a first time domain to a second (core) time domain (as described in US8370543 for synchronization logic 306), would naturally look to known FIFO architectures for this purpose. The internal mechanisms of these FIFO references would provide the specific "synchronizing logic" and "synchronously clocking" capabilities required.

• US6055607A (Interface queue with bypassing capability for main storage unit) further reinforces the concept of prioritized handling of requests.

  • Motivation for "predetermined priority": While US6269413B1 provides a framework for managing multiple requests, US6055607A's "interface queue with bypassing capability" explicitly teaches mechanisms for prioritizing data flow and handling requests out of sequential order if needed. A POSA would be motivated to integrate such a bypassing or explicit priority mechanism into the "load logic" (or arbitration scheme) of the multi-FIFO system described in US6269413B1 to ensure that critical requests are serviced first, thereby achieving a "predetermined priority" output as claimed in US8370543.

Motivation for Combining:

A POSA encountering the problem of synchronizing resource access between independent time domains, especially where traditional pulse width restrictions or high-speed clocks are undesirable (as highlighted in the background of US8370543), would be motivated to combine these references for the following reasons:

1. Standard Solutions for Asynchronous Communication: FIFOs are the established and obvious choice for transferring data across asynchronous clock domains to prevent metastability and ensure data integrity. Therefore, incorporating the synchronization mechanisms from US4965794A or US5898893A into any system requiring clock domain crossing, such as the multi-resource access system of US6269413B1, would be a matter of routine engineering design.
2. Efficient Resource Management: When multiple requests are vying for a shared resource, as enabled by US6269413B1's multiple logical FIFOs accessing a single memory, an arbitration scheme is essential. Implementing a "predetermined priority" (as found in US6055607A and also a common design principle in resource arbiters) for outputting these requests would be a logical and desirable design choice to optimize performance, prevent deadlocks, and ensure quality of service for critical operations.
3. No Unforeseen Results: Combining these known elements in this manner would yield predictable results: a system that can receive and latch asynchronous requests, synchronize them to a target clock domain, and then dispatch them to a shared resource based on a defined priority, without requiring stringent pulse width controls or excessively fast clocks. This directly addresses the stated problems in the background of US8370543 with conventional synchronization designs.

Conclusion

Therefore, a person having ordinary skill in the art, seeking to synchronize device resource access information between independent time domains and manage resource requests efficiently, would have been motivated to combine the teachings of US6269413B1 (for managing multiple requests and providing a framework for outputting them), US4965794A or US5898893A (for explicit clock domain synchronization), and US6055607A (for implementing a predetermined priority scheme). This combination would render the independent claims (Claims 1, 9, and 16) of US patent 8,370,543 obvious.