Patent 8329572

Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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The USPTO database can be used to identify prior art for US patent 8329572. Prior art includes information publicly known before the effective filing date of a U.S. patent application, such as U.S. and foreign patents, published patent applications, and various publications.

A direct search for US patent 8329572 in the USPTO database for prior art will involve looking at the "Cited By" and "References Cited" sections of the patent document itself. However, the provided content for US8329572B2 does not explicitly list these sections. To identify the most relevant prior art and related details (full citation, publication/filing date, brief description, and potential anticipation under 35 U.S.C. § 102), direct access to the full patent document from the USPTO website or a similar patent database (like Google Patents which was used to fetch the current document) is needed.

Based on the information within the provided patent text, which discusses the "Description of Related Art," the patent itself identifies existing problems with conventional semiconductor devices. These problems serve as the context for the invention and implicitly refer to the state of the art that existed before this patent.

The patent highlights the following issues with prior art:

  • Corrosion of interconnect layers: In conventional damascene processes for copper interconnects, during the etching of holes (vias) and trenches (like seal rings), if the underlying interconnect layer is exposed before ashing or polymer removal, the metal corrodes. This occurs because etching rates increase with opening area, causing larger trenches to etch deeper and potentially expose the interconnect layer prematurely.
  • Non-uniform etching with multiple hole patterns: When forming multiple types of hole patterns with different pattern densities, it's difficult to achieve uniform etching depths. This can lead to the interconnect layer being exposed in some areas.

The invention directly addresses these problems with its proposed semiconductor device structures and fabrication methods. The prior art in this context would be the conventional damascene processes and semiconductor device structures that exhibit these specific corrosion and non-uniform etching issues. Without the explicit "References Cited" section, I cannot provide specific patent numbers and full citations for the prior art considered by the examiner during the prosecution of US8329572.

Generated 5/20/2026, 6:46:35 AM