Prior art

Analysis of Prior Art Cited in U.S. Patent 8,307,116

A thorough review of the prior art cited during the prosecution of U.S. Patent 8,307,116, "Scalable bus-based on-chip interconnection networks," provides insight into the technological landscape at the time of the invention and helps to delineate the novel aspects of the patented technology. The following analysis details the most relevant references cited by the examiner and their potential relationship to the claims of the '116 patent.

Key Cited U.S. Patents:

• U.S. Patent No. 7,490,207 B2: "Interconnect for a Multi-Processor Integrated Circuit"

  • Publication Date: February 10, 2009 (Filed: June 29, 2004)
  • Description: This patent, assigned to Intel Corporation, describes a point-to-point bus interconnect for a multi-processor system on a single integrated circuit. It details a system with multiple processor cores, cache memory, and an interconnect fabric. The interconnect is designed to facilitate communication between the various components on the chip.
  • Potential Anticipation of Claims: The '207 patent discloses a multi-nodal system with a network of communication channels. This could be seen as relevant to the preamble of claims 1, 8, and 14, which describe a "multinodal array having a plurality of nodes" and "a plurality of physical communication channels." However, the '207 patent focuses on a ring-based topology and does not explicitly teach the specific grid-like structure where the number of channels in a row or column equals the number of nodes, nor the "maximum of two hops" routing efficiency, which are key limitations of the '116 patent's independent claims.

• U.S. Patent No. 7,386,679 B1: "Method and Apparatus for a Scalable and Modular Interconnect for a Multi-Core Processor"

  • Publication Date: June 10, 2008 (Filed: September 29, 2005)
  • Description: Assigned to Sun Microsystems, this patent discloses a scalable and modular interconnect for a multi-core processor. It describes a crossbar switch architecture that allows for high-throughput communication between multiple processor cores. The focus is on providing a high-bandwidth, low-latency interconnect.
  • Potential Anticipation of Claims: The '679 patent's disclosure of a multi-core processor with an interconnect architecture is broadly relevant to the subject matter of the '116 patent. It addresses the general problem of on-chip communication. However, it does not appear to describe the specific two-dimensional array structure with a defined relationship between the number of nodes and communication channels per row/column, nor the two-hop routing limitation as claimed in the '116 patent.

• U.S. Patent No. 7,203,778 B2: "Scalable Interconnect Architecture"

  • Publication Date: April 10, 2007 (Filed: December 16, 2002)
  • Description: This patent, assigned to Intel Corporation, details a scalable interconnect architecture for coupling multiple processing agents. It describes a network of interconnected switches and links that can be configured in various topologies, including a mesh. The architecture aims to provide high-performance communication for multi-processor systems.
  • Potential Anticipation of Claims: The '778 patent's description of a scalable mesh-like interconnect is highly relevant. It anticipates the general concept of a grid of nodes and communication channels. However, a detailed analysis would be required to determine if it explicitly teaches the "one channel per node" in each row/column configuration and the guaranteed "maximum of two hops" routing that are central to the novelty of the '116 patent's claims.

• U.S. Patent No. 6,854,019 B2: "System and Method for Routing Messages in a Parallel Computer"

  • Publication Date: February 8, 2005 (Filed: January 14, 2002)
  • Description: This patent describes a method for routing messages in a parallel computer system with a multi-dimensional mesh or torus interconnect topology. It focuses on routing algorithms and techniques for efficient data transfer in such networks.
  • Potential Anticipation of Claims: This reference is pertinent to the general field of routing in parallel processing systems. It likely discusses concepts of "hops" and efficient data paths. However, it may not describe the specific hardware architecture of the '116 patent, particularly the configuration where a single physical communication channel can route data to two or more destination nodes simultaneously and the strict two-hop maximum between any two nodes in the array.

• U.S. Patent No. 8,024,510 B2: "Re-Routing Data in a System-on-a-Chip to Avoid Congestion"

  • Publication Date: September 20, 2011 (Filed: June 30, 2006)
  • Description: This patent, assigned to IBM, focuses on methods for dynamically re-routing data packets in a network-on-chip to avoid congestion. It describes a system with routers and communication links and a mechanism for selecting alternative paths when a primary path is busy.
  • Potential Anticipation of Claims: While dealing with on-chip networks, the '510 patent's primary focus is on congestion control rather than the fundamental network topology and its inherent routing efficiency. It does not appear to disclose the specific structural characteristics of the '116 patent's claims, such as the one-to-one correspondence between nodes and channels per row/column or the two-hop routing guarantee.

Cited U.S. Patent Application Publications:

• U.S. Patent Application Publication No. 2005/0138290 A1: "Multi-Core Processor with Cross-Bar Switch Interconnect"

  • Publication Date: June 23, 2005 (Filed: December 23, 2003)
  • Description: This application describes a multi-core processor architecture that utilizes a crossbar switch for interconnecting the cores. The focus is on a high-speed, non-blocking interconnect.
  • Potential Anticipation of Claims: Similar to the '679 patent, this application discloses a multi-core interconnect but centers on a crossbar architecture. This is a different approach to the distributed, bus-based network described in the '116 patent and is unlikely to anticipate the specific claims related to the row/column channel configuration and two-hop routing.

• U.S. Patent Application Publication No. 2007/0011409 A1: "System and Method for Managing Communications in a Multiprocessor System"

  • Publication Date: January 11, 2007 (Filed: July 8, 2005)
  • Description: This application details a communication management system for a multiprocessor environment. It describes a network-on-chip with routers and links and methods for handling data packets and managing traffic flow.
  • Potential Anticipation of Claims: This publication is relevant to the broader context of on-chip communication. However, its claims and description focus more on the management and protocol aspects of the network rather than the specific physical topology and its inherent low-latency properties as claimed in the '116 patent.

In summary, while the cited prior art establishes a background of multi-core and on-chip network architectures, none of the references appear to explicitly disclose the combination of features that define the core invention of U.S. Patent 8,307,116. Specifically, the novel aspects appear to be the unique grid-based topology where the number of communication channels in a given dimension (row or column) is equal to the number of nodes in that dimension, and the resulting architectural guarantee that any node can communicate with any other node in a maximum of two hops. The litigation with Intel Corporation, centered on this "maximum of two hops" feature, suggests that this is the key point of contention and perceived novelty of the '116 patent.