Obviousness

Obviousness Analysis of U.S. Patent 8,307,116

An analysis of U.S. Patent No. 8,307,116 ("the '116 patent") in light of the prior art cited during its prosecution suggests that its claims may be vulnerable to an obviousness challenge under 35 U.S.C. § 103. A person of ordinary skill in the art (POSITA) at the time of the invention (around 2009), working in the field of on-chip network design, would have been aware of the pressing need to improve the scalability and efficiency of interconnects for the increasing number of cores in multi-processor systems-on-chip (MPSoCs). The key inventive concept of the '116 patent—a grid-like network topology guaranteeing a maximum of two hops between any two nodes—could be argued as an obvious combination of known design principles and architectural elements present in the prior art.

The primary argument for obviousness rests on combining a base architecture, such as a mesh or grid interconnect, with established principles of bus-based communication and routing strategies aimed at minimizing latency.

The Independent Claims of U.S. Patent 8,307,116

A detailed review of the independent claims (1, 8, and 14) reveals the core elements of the invention:

1. A multinodal array (on-chip network) of processing nodes.
2. A plurality of physical communication channels connecting the nodes.
3. A specific grid topology: The channels are arranged in horizontal and vertical rows.
4. A specific channel-to-node ratio: The number of channels in a given row (horizontal or vertical) is equal to the number of nodes in that row.
5. Shared-medium or broadcast capability: At least one channel is configured to route data from a single source node to "two or more other destination nodes." This implies a bus-like or multicast functionality, rather than a purely point-to-point connection.
6. A maximum two-hop latency: The entire network is arranged to ensure that data can travel between any two nodes in, at most, two hops.

Potential Obviousness Combinations

1. Combination of Intel's '778 Patent and Broadcast/Bus Principles:

• Primary Reference: U.S. Patent No. 7,203,778 ("Scalable Interconnect Architecture")
  The '778 patent, assigned to Intel, serves as a strong foundational reference. It explicitly discloses a scalable interconnect architecture for multi-processor systems, which can be configured in a mesh topology (see Fig. 1 and Col. 3, lines 45-55 of '778 patent). This directly teaches the concept of a multinodal array with nodes arranged in rows and columns, connected by communication links, satisfying elements 1, 2, and 3 of the '116 patent's claims. The '778 patent's goal is to provide a high-performance, scalable communication fabric, a common objective in the field.

• Motivation to Combine with Known Bus Architectures:
  A POSITA, starting with the mesh architecture of the '778 patent, would be motivated to optimize it for latency and wire-count, two of the most critical constraints in on-chip network design. A known trade-off in network design is between dedicated point-to-point links (high wire-count, potential for many hops in a large mesh) and shared buses (lower wire-count, broadcast capability). The '116 patent's solution is a hybrid, using shared, row-level and column-level buses.

  A POSITA would find it obvious to implement the communication channels in the '778 patent's mesh as shared buses rather than point-to-point links to reduce complexity and facilitate broadcast or multicast operations, which are common in cache coherency protocols and other parallel computing tasks. This modification directly leads to element 5 of the '116 claims.

  Once the communication channels are implemented as shared row/column buses, the "maximum of two hops" characteristic (element 6) becomes a natural and predictable result of the topology. To get from any source node to any destination node in the grid, a data packet would take one hop on its source row bus to reach the correct column, and a second hop on the destination column bus to reach the target node. This "X-Y routing" on a bus-based grid is a well-understood routing algorithm. Therefore, the two-hop limit is not an unexpected discovery but a direct consequence of combining a mesh layout with shared-bus channels.

2. Combination of Sun Microsystems' '679 Patent and General Network Design Principles:

• Primary Reference: U.S. Patent No. 7,386,679 ("Method and Apparatus for a Scalable and Modular Interconnect for a Multi-Core Processor")
  The '679 patent describes a scalable, high-bandwidth interconnect for multi-core processors. While it emphasizes a crossbar switch, it addresses the fundamental problem of connecting numerous cores efficiently. The motivation is to overcome the limitations of traditional shared-bus architectures that create performance bottlenecks.

• Motivation to Modify for Scalability and Reduced Complexity:
  A POSITA would recognize that a full crossbar switch, while offering low latency, becomes prohibitively complex and power-hungry as the number of nodes increases. A common design strategy to address this is to use a distributed or segmented network, such as a mesh. It would have been obvious to apply the principles of scalable interconnects from the '679 patent to a more physically regular and scalable topology like a 2D mesh or grid, as was common in the field.

  This leads to a similar architecture as described in the '116 patent. By arranging the nodes in a grid and providing dedicated communication channels for each row and column (element 4), a POSITA could achieve a balance between the high connectivity of a crossbar and the scalability of a mesh. The idea of a single channel routing to multiple destinations (element 5) is inherent in a bus-based implementation, which would be a logical alternative to the complex switching fabric of a pure crossbar. As in the first example, the two-hop routing (element 6) is an inherent and foreseeable advantage of this architectural choice.

Conclusion on Obviousness

The claims of U.S. Patent 8,307,116 appear to describe a specific implementation of a flattened butterfly or concentrated mesh topology using shared buses. While the combination of features results in an efficient network, the individual elements—grid-based arrays, row/column communication channels, shared bus structures, and X-Y routing—were all well-known concepts in the field of computer architecture and on-chip networks prior to 2009.

The inventive step, as claimed, seems to lie in the specific combination that guarantees a two-hop maximum latency. However, a POSITA tasked with designing a low-latency interconnect for a many-core chip would naturally explore grid-based topologies. The decision to use shared buses for each row and column, as a way to manage wire routing complexity and support multicast, would directly and predictably lead to the two-hop routing characteristic. Therefore, it is highly probable that the claimed invention would have been considered an obvious design choice to one of ordinary skill in the art at the time of the invention. The ongoing litigation against Intel, which utilizes a mesh architecture, will likely hinge on whether Intel can successfully argue that this specific combination and its resulting performance were obvious developments in the field.