Prior art

To identify the most relevant prior art for US patent 8234483, I will examine the patent's own cited references as listed on Google Patents, as these are the documents the examiner and inventor considered during prosecution. The information provided in the prompt's "Obviousness" section already lists these citations, which are key for identifying potentially anticipatory prior art under 35 U.S.C. § 102.

Here's an analysis of the patent citations and their potential relevance to anticipating the claims of US8234483:

Cited Prior Art and Potential Anticipation

The patent US8234483 itself lists several prior art references in its "Cited By (Examiner)" and "Patent Citations" sections. For clarity, I will focus on the most relevant references directly discussed in the "Obviousness" section of the provided context, which are explicitly presented as foundational for the invention's background.

1. US5613071A: Method and apparatus for providing remote memory access in a distributed memory multiprocessor system

• Full Citation: US5613071A
• Publication/Filing Date: Filed: 1995-07-14 / Granted: 1997-03-18
• Brief Description: This patent by Intel Corporation describes a method and apparatus for remote memory access in a distributed memory multiprocessor system. It focuses on providing efficient access to memory that is not locally attached to a processor.
• Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This patent establishes the concept of remote memory access in a multiprocessor system, which is a foundational element. However, it does not explicitly detail the packet-switched serial interface as a co-located component with the memory and its specific encapsulation/decapsulation functions as defined in Claim 1 of US8234483. It might provide context for the general problem of memory access, but its detailed anticipation of the specific mechanism in US8234483 is less direct without further analysis of its communication protocols.

2. US20040019704A1: Multiple processor integrated circuit having configurable packet-based interfaces

• Full Citation: US20040019704A1
• Publication/Filing Date: Filed: 2002-05-15 / Published: 2004-01-29
• Brief Description: This patent application by Barton Sano describes a multiple processor integrated circuit with configurable packet-based interfaces. It addresses using packet-based communication within an integrated circuit environment.
• Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference is highly relevant. It explicitly teaches an "integrated circuit having configurable packet-based interfaces" and "multiple processors." This directly bears on the "packet processor" and "high-speed packet switched serial interface" aspects of Claim 1 of US8234483, especially the use of packets for communication within a chip. If the interfaces described are serial and are used for memory access in a manner that includes decapsulation/encapsulation, it could potentially anticipate Claim 1 and its dependent method/computer-readable media claims (Claims 6 and 11). The degree of anticipation would depend on whether it teaches the specific co-location of the packet processor with the memory device on the same semiconductor die and the explicit function of decapsulating address, data and control information for memory access.

3. US6850998B2: Disk array system and a method for controlling the disk array system

• Full Citation: US6850998B2
• Publication/Filing Date: Filed: 2001-09-06 / Granted: 2005-02-01
• Brief Description: This patent by Hitachi, Ltd. concerns a disk array system and its control method. It deals with data management and access in storage systems.
• Potential Anticipated Claim(s) (under 35 U.S.C. § 102): While this patent deals with data access in storage systems, its primary focus on disk arrays makes it less directly relevant to the processor-memory interface with an integrated packet processor on a semiconductor die for main memory access as described in US8234483. It is unlikely to anticipate Claim 1 directly as it operates in a different functional domain (disk storage vs. processor-main memory).

4. US6928505B1: USB device controller

• Full Citation: US6928505B1
• Publication/Filing Date: Filed: 1998-11-12 / Granted: 2005-08-09
• Brief Description: This patent by Edwin E. Klingman describes a USB device controller.
• Potential Anticipated Claim(s) (under 35 U.S.C. § 102): A USB device controller manages serial communication, but it is typically for peripheral devices and does not address the core problem of high-speed processor-to-main memory access with co-located packet processors on a semiconductor die, as claimed in US8234483. It is unlikely to anticipate Claim 1.

5. US7352763B2: Device to receive, buffer, and transmit packets of data in a packet switching network

• Full Citation: US7352763B2
• Publication/Filing Date: Filed: 2000-06-26 / Granted: 2008-04-01
• Brief Description: This Intel Corporation patent describes a device for receiving, buffering, and transmitting data packets in a packet switching network.
• Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This patent is very relevant as it deals with "packet switching networks" and "receiving, buffering, and transmitting packets." It could potentially anticipate elements of Claim 1, particularly the general concept of a packet processor handling packetized data. The key differentiating factor for US8234483 would be the explicit co-location with the memory device on a semiconductor die and the specific function of decapsulating memory address and control information for direct memory access, rather than just general network packet handling. Further analysis would be needed to see if it teaches all limitations of Claim 1.

6. US7848825B2: Master/slave mode for sensor processing devices

• Full Citation: US7848825B2
• Publication/Filing Date: Filed: 2007-01-03 / Granted: 2010-12-07
• Brief Description: This [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) patent relates to master/slave mode operation for sensor processing devices.
• Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This patent's focus on sensor processing devices and master/slave modes appears unrelated to the core aspects of packet-switched serial interfaces for processor-memory access as claimed in US8234483. It is unlikely to anticipate Claim 1.

Most Relevant Prior Art for Anticipation (under 35 U.S.C. § 102):

Based on the descriptions, US20040019704A1 (Multiple processor integrated circuit having configurable packet-based interfaces) and US7352763B2 (Device to receive, buffer, and transmit packets of data in a packet switching network) are the most likely candidates to potentially anticipate elements of Claim 1 of US8234483.

• US20040019704A1 is particularly strong because it describes packet-based interfaces within an integrated circuit for multiple processors, which directly relates to the context of US8234483. The extent of anticipation hinges on whether it explicitly teaches the co-location of a packet processor with memory on a semiconductor die for providing read/write access via decapsulation/encapsulation of memory access specific information.
• US7352763B2 covers the general operation of packet processing in a network. Its anticipatory strength would depend on whether this general packet handling device is also taught to be co-located with memory on a die and configured for memory access requests (address, data, control) via decapsulation and encapsulation.