Obviousness

Obviousness Analysis (35 U.S.C. § 103) for US8234483

This analysis identifies combinations of prior art references that would render the claims of US patent 8234483 obvious to a person having ordinary skill in the art (POSA) at the time of the invention (priority date 2007-02-02), and articulates the motivation for such combinations.

The independent claims of US8234483 (Claims 1, 6, and 11) focus on a chip architecture where a packet processor is co-located with a memory device on a semiconductor die. This packet processor decapsulates serial packetized memory access requests (address, data, control) from an external device and encapsulates responses back to the external device, all via a high-speed packet switched serial interface.

Claim 1: Apparatus Obviousness

Combination 1: US20040019704A1 (Sano) in view of general knowledge of packet processing and serial interfaces.

• US20040019704A1 (Sano): This reference discloses a "multiple processor integrated circuit having configurable packet-based interfaces". Sano teaches using packet-based communication within an integrated circuit environment for communication between processors. This reference provides the core concept of packet-based interfaces on a chip.

  • Sano explicitly teaches an "integrated circuit having configurable packet-based interfaces" and "multiple processors". This covers the "semiconductor die package" and "packet processor" aspects of Claim 1 in a broad sense, and packet-based communication within the chip.
  • It also teaches "configurable" interfaces, implying the ability to define packet protocols.

• Motivation to Combine/Modifications: A POSA, seeking to improve processor-memory communication efficiency and overcome the "memory wall" or "memory gap" problem (as described in the background of US8234483), would have been motivated to apply Sano's packet-based on-chip communication to memory access. The background of US8234483 itself notes that the "memory gap problem is further compounded by the need to address a large memory capacity" and that "One solution employed in the prior art to overcome the memory wall/memory gap problem is to eliminate the parallel bus interface between the processor and memory and use a serial backplane interface instead of a parallel bus". This highlights a recognized problem and a known general solution (serial interfaces).

  • Co-location of packet processor with memory: Given that Sano teaches packet-based interfaces on an integrated circuit with multiple processors, a POSA would readily extend this to include memory devices (which are fundamental components in any processor system) co-located on the same die or package. This is a logical design choice to minimize latency and improve performance by bringing the interface logic closer to the resource it serves, consistent with the objective of addressing the memory wall problem.
  • High-speed packet switched serial interface: The background of US8234483 also highlights the trend of migrating to serial interfaces for I/O and backplanes due to the limitations of parallel buses at high speeds. The combination of packet-based communication (Sano) with high-speed serial interconnects was a known trend in computing architectures (e.g., PCI-Express, Infiniband, Gigabit Ethernet, all mentioned in the background of US8234483 as "industry standard I/O protocols" or "hierarchical packet-based interconnection fabric"). A POSA would have known to implement the packet-based interfaces taught by Sano using a high-speed serial connection to achieve the performance benefits desired for memory access.
  • Decapsulating/Encapsulating memory access information: The functions of decapsulating address, data, and control information from a packet and encapsulating response data into another packet are standard operations for any packet-based communication system interfacing with a resource. When adapting a packet-based interface for memory access, it would be obvious to a POSA to define a packet format that includes memory address, data, and control commands (like Read/Write) and to implement logic to extract (decapsulate) and insert (encapsulate) this information. This is a routine engineering design choice for communicating with memory over a packet-switched medium.

Conclusion for Claim 1: US20040019704A1, combined with the general knowledge in the art regarding the advantages of high-speed serial communication, the need to address the memory wall problem, and standard packet processing techniques for resource access, would render Claim 1 obvious.

Claim 6: Method Obviousness

Combination 1: The method inherent in the apparatus of Claim 1, as rendered obvious by US20040019704A1 and general knowledge.

• Claim 6 describes a method comprising steps that directly correspond to the functions of the apparatus in Claim 1: "providing a semiconductor die package having co-located thereon at least one memory device with at least one packet processor...adapted to provide an external device read and write access...by decapsulating address, data and control information...and encapsulating data...".

• Motivation to Combine/Modifications: If the apparatus of Claim 1 is obvious, then the method of operating that apparatus (Claim 6) using its inherent functions would also be obvious. The steps of providing the components and utilizing the interface for decapsulating/encapsulating memory access packets are directly dictated by the structure and intended function of the obvious apparatus. It is a well-established principle that if an apparatus is obvious, the method of using that apparatus for its intended purpose is also obvious.

Conclusion for Claim 6: The method steps described in Claim 6 are the inherent functions of the apparatus described in Claim 1. Since the apparatus of Claim 1 is rendered obvious by US20040019704A1 and general knowledge, the method of Claim 6 is likewise obvious.

Claim 11: Computer Readable Media Obviousness

Combination 1: The instructions defining the apparatus and method of Claims 1 and 6, as rendered obvious.

• Claim 11 describes a computer readable media having recorded thereon "instructions defining" the components and functions of the apparatus described in Claim 1 and the method described in Claim 6.

• Motivation to Combine/Modifications: It would have been obvious for a POSA to implement the obvious apparatus and method (from Claims 1 and 6) using computer-readable instructions. The development of software or firmware to control and configure hardware components is a routine engineering task. If the underlying hardware architecture and its operational steps are obvious, then storing instructions to create or control such an architecture on computer-readable media would also be obvious. This is particularly true given the programmable nature implied by "configurable packet-based interfaces" in Sano and the "on the fly programmable bit stream processor" mentioned in US8234483's description.

Conclusion for Claim 11: As the apparatus and method of Claims 1 and 6 are obvious, generating computer-readable instructions to implement or define these obvious structures and functions would be a straightforward and obvious step for a POSA.

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Further Considerations for Dependent Claims

The dependent claims (2-5, 7-10, 12-16) add specific features such as a switch interface (Claim 2), programmable bit stream processor implementation (Claim 3), transfer to external packet-switched network (Claim 5), and implementation on FPGA/ASIC (Claims 15, 16).

• Switch Interface (Claim 2): The use of switches to mediate communication between multiple components on a chip or in a system, particularly in packet-switched networks, was well-known in the art. The background of US8234483 mentions "Advanced Switching Interconnect (ASI) switching fabrics" and other hierarchical packet-based interconnection fabrics like "Ethernet, RapidIO, PCI Express or Infiniband". US7352763B2 teaches a "device to receive, buffer, and transmit packets of data in a packet switching network", inherently implying switching capabilities. A POSA would find it obvious to integrate a switch with multiple packet processors on a die to manage traffic between them and an external port, especially in a multi-memory or multi-processor context.
• Programmable Bit Stream Processor (Claim 3): The concept of programmable logic and bit stream processors for protocol handling was also known. US20040019704A1 teaches "configurable packet-based interfaces", which suggests programmability. The general idea of using programmable components (like FPGAs, which are explicitly mentioned in Claim 15) for flexible protocol handling was a known engineering approach to adapt to various standards.
• Transfer to External Packet-Switched Network (Claim 5): The core idea of using packet-switched protocols like Ethernet for I/O and network communication was prevalent. If the on-chip memory access uses a packet-switched serial interface, it is a logical extension to use the same or compatible interface for communication with external packet-switched networks.

In conclusion, the independent claims of US8234483 are rendered obvious by combinations of existing prior art, particularly US20040019704A1, supplemented by common general knowledge in the field regarding serial communication advantages, the memory wall problem, and standard packet processing and switching techniques. The motivations for these combinations are rooted in improving system performance, addressing known bottlenecks, and integrating known elements in a logical manner to achieve predictable results.