US 8103942

I'll search for authoritative information on this patent number before summarizing.

Let me check for any litigation or CAFC activity and confirm assignee details.

Let me try to retrieve the remaining claims (the provided text truncates at claim 8; the patent has 16 claims).

US Patent 8,103,942 — Summary

Note on sourcing: The authoritative full text supplied for this analysis is the Google Patents record (fetched 2026-09-30). My web searches for litigation activity returned no results, and I could not directly query USPTO Patent Center or the CAFC docket. Specific uncertainties are flagged below.

Bibliographic data

Abstract (as issued)

A data transmission apparatus includes a packet generation section, a frame encoding section, a transmission section, a reception section, a frame decoding section and a packet extraction section. The packet generation section generates a packet upon request. The frame encoding section generates a frame of predetermined length by dividing the packet or adding dummy data, and generates an error-correcting-code-added frame by adding an error correcting code to the frame. The transmission section transmits the error-correcting-code-added frame over a transmission line. The reception section receives it. The frame decoding section performs error detection and correction on the frame. The packet extraction section extracts the packet by removing the ECC from the corrected frame.

Plain-language overview of the independent claim(s)

Claim 1 — a "data transmission apparatus" (independent). The claim covers a bidirectional, high-speed serial link on a single apparatus that does six things:

1. Generates a packet on request (packet generation section);
2. Builds a fixed-length frame from the packet (splitting it or padding with dummy data) and adds an error-correcting code to produce an "error-correcting-code-added frame" (frame encoding section);
3. Transmits that frame over a transmission line (transmission section);
4. Receives such a frame over the transmission line (reception section);
5. Performs error detection and correction on the received frame (frame decoding section); and
6. Extracts the original packet by stripping the ECC (packet extraction section).

The claim then recites the internal structure of two of those blocks:

• Frame encoding section comprises a frame forming section (forms the fixed-length frame), a DC balance converting section (e.g., 8B10B coding — the spec notes 4B5B or 64B66B as alternatives), and an ECC adding section that adds the ECC after the DC-balance conversion and hands the frame to the transmitter.
• Frame decoding section comprises an error detection/correction section, an ECC removing section, and a DC inverse balance converting section (e.g., 10B8B) that outputs the recovered frame to the packet extractor.

The key limitation is not merely "add an ECC": it is the ordering — ECC is computed over the DC-balanced (encoded) frame, and the inverse DC-balance conversion is performed only after the ECC has been stripped. In the first exemplary embodiment this yields an 80-bit 8B10B-encoded frame plus an 8-bit ECC (plus inversion and 2-bit delimiters) = a 100-bit ECC frame, sent five 20-bit words per frame. The second exemplary embodiment instead uses a horizontal ECC plus a diagonal ECC across a time-series array of 8 frames (8 blocks of 10 bits each) = a 120-bit frame, allowing two-dimensional correction with a claimed residual uncorrectable-error probability on the order of 10⁻⁴⁰. Dependent claims add features such as placing a control symbol with Hamming distance ≥ 2 from the clock-compensation control symbol at the head of the first frame after a clock compensation sequence, distinguishing the ECC from other control symbols, and idle-symbol-based clock compensation with single-bit-error tolerance.

Other independent claims — flagged uncertainty. The Google Patents record states "Claims (16)," but the copy supplied to me is truncated at the end of claim 8, so I cannot authoritatively reproduce claims 9–16. Consistent with the title and with secondary sources (Justia's rendering of the US 2008/0294966 disclosure), the claim set appears to include at least one further independent claim directed to a "data transmission device" (transmit-side-only variant), and, given the title, likely independent claims to a "data reception device" (receive-side-only variant) and a "data transmission system" (transmitter + transmission line + receiver). I do not have the verbatim text of those claims and cannot confirm their exact scope or numbering. Treat the paragraph above as an inference, not a verified claim listing.

Compliance with the requested searches

• USPTO database: I was unable to query Patent Center directly. The bibliographic data above comes from the Google Patents record of US 8,103,942 B2, which mirrors USPTO front-page data (application 12/055,474, granted 2012-01-24). No contradicting data appeared in search results.
• CAFC 2026 dockets: My searches returned no evidence of any 2026 CAFC appeal, IPR, or district-court litigation involving patent 8,103,942. This is a negative search result, not a positive confirmation that no such proceeding exists — docket databases are not fully indexed by general web search, so I cannot certify the absence of litigation. USPTO records list the patent as expired for failure to pay maintenance fees (adjusted expiration 2030-11-24), which makes active assertion unlikely but is not dispositive.

I have intentionally reported only the single patent number requested; no results for similar or adjacent numbers (e.g., 8,106,444, which appeared incidentally in search noise) are included.

I'll research litigation involving US patent 8103942.

Let me refine my search with more targeted queries.

Let me try more targeted litigation databases and patent-specific searches.

I'll verify the structured data against live sources before concluding.

PTAB proceedings overview

Zero AIA trial proceedings on file. The USPTO Open Data Portal returns no IPR, PGR, or CBM proceeding for US 8,103,942 as of the most recent ingest, and independent web searches (Google Patents, PTAB decision repositories, litigation coverage) surfaced no petition, institution decision, final written decision, or Federal Circuit appeal naming this patent. The bottom-line defensive posture is therefore "challenge never tested at the PTAB" — this is not a hardened patent that has survived adversarial review; it is an untested one. It is a 2007-priority, 16-claim Fuji Xerox (now Fujifilm Business Innovation) patent covering 8B10B-coded ECC frames over a serial link (claim 1), with a second embodiment (claims 6–8) adding horizontal + diagonal ECCs — no petitioner has ever attacked it.

No proceedings to enumerate

Because the structured data block contains no AIA trial proceeding records, there is no proceeding number, petitioner, panel, petition ground, institution ruling, final written decision, settlement, or appeal to report. Per the operating constraint against fabricating proceeding numbers, I am not creating entries here. For completeness, the reason no proceeding is likely to exist is visible in the patent's own record:

• US 8,103,942 B2 (application 12/055,474) — Data transmission apparatus, data transmission device, data reception device and data transmission system; inventors Norihiko Kuroishi, Takeshi Kamimura, Seiji Suzuki, Jun Kitamura, Nobuo Mori, Manabu Akamatsu, Kunihiro Seno; original assignee Fuji Xerox Co., Ltd.; current assignee Fujifilm Business Innovation Corp. Source: Google Patents US8103942B2.
• Priority date: 2007-05-24 (JP 2007-138255) and 2007-09-04 (JP 2007-228981).
• Filed: 2008-03-26. Granted: 2012-01-24. Term: expired (fee-related lapse), with an adjusted expiration date of 2030-11-24 listed in the record.
• Claims: 16 total. Claim 1 is the core independent claim (packet generation → fixed-length frame → DC balance conversion → ECC add → transmit; receive → ECC detect/correct → ECC removal → DC inverse balance conversion → packet extraction). Claim 6 is a separate independent claim directed to the horizontal/diagonal ECC embodiment; claims 2–5 and 7–8 depend from those.

Strategic summary

Claim status. Because no PTAB proceeding exists, no claim of US 8,103,942 has been canceled, disclaimed through an IPR, or held unpatentable by the Board. All 16 claims nominally remain as granted — UNTESTED in every adversarial posture. Nothing has been narrowed by the PTAB; the only scope-limiting events in the file are ordinary prosecution and the issuance of the patent itself. If a defendant is being told claims 1–5 "have been canceled," that representation is false on this record — those are the very claims that were never challenged. (Note the claims-invalidated/unpatentability assertions that a search turns up for a "’394 patent" belong to Corning's glass patent, a different patent entirely — do not confuse the two.)

Estoppel landscape. With no FWD, there is no § 315(e)(2) estoppel running against anyone, and no petitioner whose prior-art grounds have been burned. A defendant today faces no IPR-based estoppel restriction and retains the full universe of § 102/§ 103 art plus § 112 and § 101 theories. Conversely, a defendant who does file an IPR takes on § 315(e) estoppel risk itself once the trial reaches FWD.

Pattern signals. No serial-petitioner pattern exists (there are no petitioners). No defensive aggregator (Unified Patents or similar) appears anywhere in the chain of title or in the assertion history. The patent has changed hands only by corporate reorganization: Fuji Xerox → Fujifilm Business Innovation Corp. It has never been the subject of a publicized assertion campaign that drew a third-party validity challenge — which is itself the likely explanation for the total absence of PTAB activity.

Practical reality check on the term. Before building any defense around claim scope, confirm the fee status. The record lists the patent as Expired - Fee Related with an adjusted expiration of 2030-11-24. If maintenance fees were in fact not paid and the lapse is not revived, the patent is unenforceable today regardless of claim validity, and the IPR question is academic. Verify current status through USPTO Patent Center for application 12/055,474 and the assignment/maintenance-fee record before relying on either the "expired" label or the nominal term.

Recommended next steps

• If a demand letter or complaint cites this patent, attack the term first. The Google Patents legal-status line ("Expired - Fee Related") is only an assumption-generating label; pull the maintenance-fee payment history in Patent Center to confirm whether the patent lapsed and whether any petition to revive was granted. If it lapsed, that is a complete defense that costs far less than an IPR.
• Do not assume the patent is "hardened" because no IPR was filed. The absence of PTAB activity here likely signals low commercial assertion value or short remaining life, not invulnerability. There is no FWD to point to and no claim to quote as invalidated.
• If you do elect an IPR (e.g., the patent is revived and asserted), note the statutory constraints: an IPR petition must be filed within one year of service of an infringement complaint (§ 315(b)), may only raise §§ 102/103 over patents and printed publications (§ 311(b)), and now faces the 2025 discretionary-denial regime (bifurcated institution, expanded Fintiv/"settled expectations" gatekeeping, Director-level institution control) described for patents of this age. Budget the full statutory clock: institution decision at ~6 months, FWD within 1 year of institution.
• Because there is no PTAB record, say so plainly in any opinion or client memo — and link the primary source rather than a secondary summary: Google Patents US8103942B2. For confirmation of the absence of AIA trials, query USPTO Patent Trial and Appeal Board E2E / PTAB Decisions and CourtListener for any Federal Circuit docket naming the patent; my searches returned nothing on either.

Caveat on data freshness: the "no proceedings" conclusion rests on the USPTO ODP structured block supplied in this prompt plus the searches run today (2026-09-30). ODP ingest can lag recently filed petitions. If you have reason to believe a petition was filed in the last month or two, re-query the PTAB API directly and PTAB E2E before finalizing.

I'll research the assignment record for US 8103942 across the available sources before writing up.

Let me check for litigation/assertion history and any recorded reassignment beyond the original.

Let me make one more targeted check for any recorded post-issuance assignment or litigation involving this patent.

Ownership & Assignment Reconstruction — US 8,103,942 B2

Patent: US 8,103,942 B2 ("Data transmission apparatus, data transmission device, data reception device and data transmission system")
Application: 12/055,474 • Filed: 2008-03-26 • Issued: 2012-01-24
Status: Expired – Fee Related (nominal adjusted expiration 2030-11-24)
Verification link: https://assignmentcenter.uspto.gov/ (search "8103942") — also https://patents.google.com/patent/US8103942/en (Legal Events tab)

⚠️ Data-access caveat up front: I was unable to open the live USPTO Assignment Center / Patent Assignment Search record for this patent during this session. The reel/frame numbers and the correspondent of record are therefore not retrievable from my sources and I will not invent them. Everything below is grounded in the Google Patents legal-events table (which mirrors USPTO assignment data), the printed front matter of the patent, and the corporate record. Where a field is unknown I say so.

Inventors

Seven named inventors, all listed on the face of US 8,103,942:

Pattern notes: This is a routine corporate-employee invention assignment — all seven assignors signed a single "ASSIGNMENT OF ASSIGNORS INTEREST" to the employer, recorded 2008-03-31, one week after the 2008-03-26 filing (see Assignment timeline). A seven-inventor team is unremarkable for a Japanese corporate serial-link / storage-controller filing. There is no evidence of inventors departing the original assignee within 12 months of filing — nothing in the record indicates a pre-fire-sale exodus. No individually-owned continuation or reissue by the inventors appears in the family.

Original assignee

Fuji Xerox Co., Ltd. (Tokyo, JP) — named on the issued patent and on the published application US 2008/0294966 A1.

• Primary business: Operating company; the Japan/Asia-Pacific copier, multifunction-printer (MFP), printer, and document-services manufacturer. Established 1962 as a joint venture between Fuji Photo Film (now FUJIFILM Holdings) and Rank Xerox / Xerox Limited.
• Product embodiment: The specification is a component-level serial-transmission architecture — an 8B10B-coded, ECC-protected packet link between a host-bus interface (2) and a memory controller (4) over a PCI Express-style line inside a semiconductor disk device (see FIG. 1 and claim 1's packet-generation / frame-encoding / ECC chain). Fuji Xerox was an active manufacturer of controllers and imaging products in this era, so the subject matter is plausibly practiced inside its equipment, but I have no product-level evidence that a discrete commercial product was sold against these specific claims — treat "shipped a product embodying the claims" as unverified.
• Current status: Operating. Fuji Xerox Co., Ltd. was renamed FUJIFILM Business Innovation Corp. effective 2021-04-01, following Fujifilm's buy-out of Xerox's stake and the expiry of the Xerox technology agreement on 2021-03-31. It is a wholly-owned subsidiary of FUJIFILM Holdings Corporation. Google Patents lists the current assignee as Fujifilm Business Innovation Corp — the same legal entity under a new name, not a new owner. No insolvency, bankruptcy, or dissolution.

Assignment timeline

Only one recorded USPTO assignment transaction appears in the Google Patents legal-events record for this patent.

• 2008-03-31 (recorded; execution date is the same business day per the record) — Reel/Frame: not retrievable from my sources
  • Conveyance: Assignment ("ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)")
  • Assignor: Kuroishi, Norihiko; Kamimura, Takeshi; Suzuki, Seiji; Kitamura, Jun; Mori, Nobuo; Akamatsu, Manabu; Seno, Kunihiro (the seven inventors)
  • Assignee: FUJI XEROX CO., LTD., Tokyo, JP
  • Correspondent: Not retrievable. For context only (not a finding): contemporaneous Fuji Xerox US filings of this period were prosecuted through Sughrue Mion (the "SUGHRUE-265550" correspondence address appears on sister Fuji Xerox application US 2010/0296864 A1). I cannot confirm Sughrue as correspondent-of-record on this patent's assignment, so it is flagged as unverified, not asserted.
  • Context: Ordinary inventor-to-employer assignment at filing — not an acquisition, fire-sale, reorg, or securitization.

No other assignment, security agreement, merger, license, or release is recorded in the legal-events table. In particular, there is no recorded post-issuance transfer of this patent.

On the 2021 rename: effective 2021-04-01 Fuji Xerox changed its corporate name to FUJIFILM Business Innovation Corp. Google Patents reflects the new name in "Current Assignee." I could not confirm whether a USPTO "Change of Name" assignment was separately recorded for this specific patent, and no reel/frame for such a filing is available to me. If one exists it would be a name-change-only conveyance with no change in beneficial ownership.

Fee lapse: the patent is marked Expired – Fee Related, meaning one or more maintenance fees were not paid and the patent lapsed before its nominal 2030-11-24 adjusted expiration. This is a significant signal that the current owner did not regard the asset as worth maintaining, let alone asserting.

Timeline diagram

timeline
    title Ownership of US 8103942
    2007 : JP priority applications filed
    2008 : US application 12/055474 filed
         : Inventors assign to Fuji Xerox
    2012 : Patent issues as US 8103942
    2021 : Fuji Xerox renamed Fujifilm Business Innovation
    2020s : Maintenance fee lapse patent expired

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The only assignment moves rights from individual inventors to their operating employer (2008-03-31). There is no transfer to any "IP / Licensing / Holdings / Ventures" LLC, no registered-agent service address, and no single-purpose entity anywhere in the chain.

2. Known asserter in the chain — not present. Neither the original assignee (Fuji Xerox) nor the current name-holder (Fujifilm Business Innovation) appears on any NPE list (Acacia, Marathon, IV, IPNav, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Innovatio, MPHJ, etc.). Both are operating manufacturers.

3. Repeat correspondent across the chain — unclear / not assessable. With a single assignment entry, the "recurrence" test cannot be run, and the correspondent of record for this patent was not retrievable. No attorney or firm is alleged here — this is a null result, not a negative finding.

4. Cascading transfers — not present. One recorded transaction in 18+ years of ownership; no chained LLCs, no shared correspondent addresses.

5. Pre-litigation transfer — not present. No assignment precedes any suit, and I found no infringement litigation naming US 8,103,942. The 2008-03-31 assignment is 4 years before issuance and is an inventor-assignment, not a litigation-enabling transfer.

6. Bankruptcy fire-sale — not present. No Chapter 7/11 proceeding of Fuji Xerox / Fujifilm Business Innovation, and no re-recorded sale of this patent. (The 2021 change was a name change under a healthy parent, FUJIFILM Holdings — not a distressed sale.)

7. Privateering — not present. No transfer to an NPE asserting on the original owner's behalf; the patent never left the corporate family.

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. It simply lapsed in place at the operating owner.

Verdict

Insufficient data (only the original assignment).

The entire recorded title chain is a single 2008-03-31 inventor-to-employer assignment to Fuji Xerox Co., Ltd. (recorded entry per Google Patents Legal Events, "ASSIGNMENT OF ASSIGNORS INTEREST"), with no subsequent transfer, no litigation, and no known-asserter involvement. The asset simply stayed with the operating manufacturer — today the same legal entity renamed FUJIFILM Business Innovation Corp. (2021-04-01) — and was allowed to lapse for non-payment of maintenance fees. Under the rubric this is not an NPE chain by any signal, but because the record contains only the original assignment it fits the "Insufficient data" verdict rather than the strictly-defined "operating-company assertion" category (which requires proof of active assertion against competitors, absent here).

Verify at: https://assignmentcenter.uspto.gov/ → search Patent Number 8103942 (to pull the exact reel/frame and correspondent of record this analysis could not retrieve), cross-checked against https://patents.google.com/patent/US8103942/en.

I'll research US patent 8103942 and its cited prior art. Let me run several searches.

Let me dig deeper into the specific citation data for this patent.

Let me try fetching the patent front page from other databases that list the referenced U.S. patents.

Summary of findings — and an important limitation

I identified the patent correctly, but I must be straightforward about a data limitation before giving you any prior-art list.

1. Patent identification (confirmed, literal)

2. The limitation — I could not retrieve the actual cited references

The task asks me to list each patent citation on the face of US 8,103,942 and map it to claims under 35 U.S.C. § 102. I cannot do that reliably from the material available to me, and I will not invent citations:

• The authoritative full text you supplied (fetched from Google Patents) contains the abstract, description, drawings list, classifications, and claims — but it does not include the "References Cited" / "Patent Citations" table ("U.S. Patent Documents" and "Foreign Patent Documents"). That table is the exact source the question requires.
• My live searches for "US8103942 references cited," the family publication US2008/0294966, and the FPO/PatentCenter records did not surface the citation table. The hits returned either the same truncated Google Patents text, or citation lists belonging to different patents (e.g., WO1999056186, WO2010123138, WO2018030350 search reports), which must not be attributed to US 8,103,942.

Because of this, any list of "references cited on US 8,103,942" I produced now would be fabricated, which your rules and mine prohibit. I'm flagging this rather than guessing.

3. What I can state with confidence

Family / priority documents (these are not prior art — they are the same invention or its priority filings):

• JP 2007‑138255 A (priority, filed 2007‑05‑24) → corresponds to JP 5233165 B2
• JP 2007‑228981 A (priority, filed 2007‑09‑04) → corresponds to JP 2009‑065255 A
• US 2008/0294966 A1 — the pre-grant publication of this same application (self, not prior art).

Technical field / "prior art keywords" indexed by the database: error, frame, section, code, correcting — i.e., ECC-protected fixed-length framing, 8B/10B DC-balance coding, and clock-compensation (IDLE) symbol handling between ECC frames.

Related Fuji Xerox contemporaneous art that search surfaced (found in other applications' search reports, not verified as citations of US 8,103,942 — treat as leads to check, not as answers):

• JP 2006‑127525 A (Fuji Xerox), 2006‑05‑18
• JP 2007‑201661 A (Fuji Xerox), 2007‑08‑09 (family: US 2007/0172123 A1; CN 101009756 A)
• JP 6‑059994 A (Fuji Xerox), 1994‑03‑04

4. Claim-mapping framework (ready to apply once the reference list is pulled)

Since claims 1 and 6 are the independent claims, § 102 anticipation must be assessed against them first:

• Claim 1 — requires the combination of: packet generation section; frame encoding section forming a fixed-length frame (dividing packet / adding dummy data) and adding an ECC; transmission section; reception section; frame decoding section (error detect + correct); packet extraction section removing the ECC; plus the internal sub-limitations — frame forming section, DC balance converting section (e.g., 8B/10B), ECC adding section; and on the receive side an error detect/correct section, ECC removing section, and DC inverse balance converting section. A § 102 reference would need every one of these elements.
• Claim 2 — control symbol ≥2 Hamming distance from the clock-compensation symbol placed in the leading portion of the first ECC frame after a clock compensation sequence.
• Claim 3 — ECC carries information distinguishing it from other control symbols.
• Claim 4 — ≥2 idle symbols per set; timing corrected when part of the set matches the idle symbol and the Hamming distance of the remainder is ≤1 bit.
• Claim 5 — idle symbol embedded within the ECC frame for clock compensation.
• Claim 6 — independent: horizontal ECC over blocks of a frame + diagonal ECC across blocks of plural time-series frames, with corresponding decode/remove steps.
• Claims 7–8 — ordering of horizontal-then-diagonal (7) or diagonal-then-horizontal (8) correction on uncorrectable error.

Note: § 102 requires a single reference disclosing all elements as arranged. Given how specific claim 1's combined DC-balance + ECC-on-encoded-frame pipeline is, the realistic risk profile for this family is generally § 103 obviousness over combinations (e.g., an 8B/10B/PCI-Express-type serial link reference combined with a conventional ECC-in-frame reference), rather than clean § 102 anticipation — but that conclusion must be tested against the actual cited references.

5. How to get the definitive answer (recommended next step)

To produce the exact citation list with § 102 mapping, retrieve the "References Cited" table from any of:

1. USPTO PatentCenter / Patent Full-Text — enter 8103942, view "Referenced By / References" and the front-page PDF.
2. Google Patents → US8103942 → the "Patent Citations" and "Cited By" tables (these exist on the page but were not returned by my search tool).
3. Espacenet / INPADOC → family + cited documents.
4. The grant front-page PDF on patentimages (the "U.S. Patent Documents" and "Foreign Patent Documents" columns).

If you can paste the "References Cited" list (or the front-page PDF text), I will immediately provide, for each reference: full citation, publication/filing date, a brief description, and the specific claim(s) it potentially anticipates under § 102, applying the framework in section 4.

Bottom line: US 8,103,942 B2 is positively identified, but its own cited-reference list was not obtainable from the authoritative text I was given, and I will not fabricate prior-art citations to fill that gap.

I'll research the actual prior-art record for this patent before building the § 103 analysis.

Let me dig into the specific prior-art references cited in this patent family.

Obviousness Analysis — US 8,103,942 B2 under 35 U.S.C. § 103

Patent: US 8,103,942 B2 ("Data transmission apparatus, data transmission device, data reception device and data transmission system"), app. US 12/055,474, filed 2008‑03‑26, earliest priority 2007‑05‑24 (JP2007138255A), second priority 2007‑09‑04 (JP2007228981A, published as JP2009065255A). Source: https://patents.google.com/patent/US8103942/en

Scope note (important, per strict‑rule compliance). The Google Patents record supplied does not contain a machine‑readable "References Cited" or "Citations" table. What the page's Prior Art section actually supplies is:

• Prior‑art date: 2007‑05‑24
• Prior‑art keywords: error, frame, section, code, correcting
• Family/priority documents: JP2007138255A → JP5233165B2; JP2007228981A → JP2009065255A
• Classifications: H03M13/29, H03M13/2906, H03M13/2921 ("…using block codes wherein error correction coding involves a diagonal direction"), H03M5/145, H04L1/0041, H04L25/4908 (mBnB codes)

I did not retrieve the USPTO IFW list of examiner‑cited references, so I will not assert a specific examiner citation list. The two Japanese documents expressly named in the family (JP 2003‑318865 and JP 2005‑512352, cited in JP5233165B2 — https://patentimages.storage.googleapis.com/9b/2c/e3/9f091f1c50d68c/JP5233165B2.pdf) plus the long‑established public art in this field form the basis below. Where I am uncertain of a reference's exact disclosure, I say so.

Because the application was filed before 2013‑03‑16, pre‑AIA § 102/§ 103 governs; the § 102(b) critical date measured from the 2007‑05‑24 priority date is 2006‑05‑24.

1. The claims at issue (elements)

Claim 1 (the only independent claim visible in the supplied text; the listing reports 16 claims, but the provided text truncates mid‑claim 8) is a combination claim of well‑trodden serial‑link building blocks:

Dependent claims add: (2) Hamming‑distant control symbol at the head of the first frame after a clock‑compensation sequence; (3) bits distinguishing the ECC from other control symbols; (4) ≥2 idle symbols as one set + Hamming‑distance‑≤1 timing correction; (5) idle symbol carried inside the ECC frame; (6…8) horizontal ECC + diagonal ECC over time‑series frames, with a specified decode order.

2. Prior art references available for combination

The patent's own classification into H03M13/2921 — "error correction coding involves a diagonal direction" is itself evidence that diagonal‑direction block coding was a populated, recognized art area before 2007, which matters for claims 6–8.

3. The primary obviousness combinations

Combination A — Claim 1

PCIe Base Spec + Widmer & Franaszek + a conventional block ECC (e.g., Hamming, JP 2005‑512352)

Every element is disclosed: PCIe supplies packet generation, serial transmit/receive and the elastic buffer; Widmer & Franaszek supplies the 8B/10B DC‑balance convert/inverse‑convert pair applied to a fixed‑length block; a block ECC applied to fixed‑length packets is taught by JP 2005‑512352 (packet ECC on fixed‑length 100‑byte packets).

Motivation. The patent's own Background concedes the design pressure — "in order to increase a transmission bandwidth, a method of increasing a bit width … or a transmission frequency may be considered … a serial bus such as a PCI express … has been dominant." A POSITA seeking to raise link reliability (lower BER, fewer ACK/NAK replays and their latency cost) on a PCIe‑class link would naturally (i) keep the mandated 8B/10B coding needed for CDR and DC balance, (ii) operate on the fixed‑length encoded block already being formed, and (iii) append a forward‑error‑correction field. KSR makes such an arrangement of known elements, each performing its known function with a predictable result, obvious.

Note the specification's own admissions, which undercut any argument that the specific selections are inventive: "a DC balance conversion method such as 4B5B or 64B66B other than the 8B10B coding may be used"; "a known correction code such as a Hamming code, a Manchester code, or a Reed‑Solomon code may be used."

Combination B — Claims 2 and 3

Combination A + PCIe/FC ordered‑set architecture (SKP ordered set; K28.5 comma) and/or XAPP581 + the known K‑character/flag conventions

• Claim 2 (NOP control symbol with Hamming distance ≥ 2 placed at the head of the first frame after the clock‑compensation sequence) is motivated by the ordinary requirement that receiver clock‑correction/ordered‑set logic must not false‑trigger on payload. The patent states the reason itself: to "prevent that data having a close Hamming distance from the IDLE symbol is arranged in data just after the IDLE symbol" (US8103942, ¶ corresponding to US20080294966A1 [0072]). That is a restatement of a known anti‑aliasing precaution, not an unexpected insight. Widmer & Franaszek's code construction already guarantees separation among special characters, and XAPP581's per‑byte mask parameters exist precisely to make sequence matching tolerant/robust.
• Claim 3 (extra bits to distinguish the ECC from other control symbols, here 2 bits plus inverted bits for DC balance) is the direct analogue of the 8B/10B K bit (Widmer & Franaszek) and of the Xilinx/Aurora TXCHARDISPMODE/TXCHARDISPVAL bit pair (XAPP581, Table 2). Once an unencoded ECC field is placed beside K28.5‑based sequences, the receiver must be able to tell them apart, and reserving flag/disparity bits is the routine way to do it — the very reason the patent gives.

Combination C — Claims 4 and 5

Combination A + PCIe SKP ordered set / FC Idle / XAPP581 clock‑correction sequences

• Claim 4: "a certain number, equal to or larger than 2, of idle symbols formed as one set," with timing correction when part of the set matches the idle symbol and the remainder differs by ≤ 1 bit. PCIe already sends a multi‑SKP ordered set for clock compensation; XAPP581 explicitly defines sequences of 2 or 4 bytes (CLK_COR_SEQ_LEN = 2 or 4). Redundancy against a single‑bit error in the compensation sequence — the patent's own stated rationale ("even if one‑bit error occurs in one cycle, there remains at least one cycle in which no bit error occurs," ¶ [0071]) — is the canonical fix for elastic‑buffer slip, and Hamming‑distance‑≤‑1 tolerance is ordinary error‑detection design.
• Claim 5 (idle symbol embedded inside the ECC frame rather than between frames) is presented by the applicant itself as an optional alternative ("Another Example of Clock Compensation Sequence," FIG. 13). Adding ECC protection to the clock‑compensation symbol removes the out‑of‑band detection constraint; a POSITA weighing "protect the symbol with the ECC" versus "keep it recognizable by the CDR/elastic buffer" would find this an obvious, predictable trade‑off (and would not expect any surprising property).

Combination D — Claims 6, 7, 8

Combination A + US 5,392,299 (Rhines) and/or JP 2005‑512352, optionally with standard product‑code/iterative‑decoding art

• Claim 6 (horizontal ECC over the blocks of one frame + diagonal ECC over blocks taken diagonally across frames arranged in time series) is squarely met by Rhines' triple orthogonally interleaved horizontal/vertical/diagonal parity over a data array, and by the two‑level "packet ECC + block ECC over plural packets" scheme attributed to JP 2005‑512352. Motivation: raising correction strength beyond one bit per frame while keeping the per‑frame ECC small — a standard reliability/overhead trade‑off.
• Claims 7 and 8 (decode by horizontal ECC first and, on an uncorrectable error, by diagonal ECC — or vice versa) are near‑dispositive of obviousness on the face of the specification, which states the order "may be configured to perform the error detection/correction operation based on the horizontal ECC after performing … based on the diagonal ECC," and that the two "may be performed alternately plural times." Where the applicant treats the claimed sequence as interchangeable with the unclaimed one, the ordering cannot supply the inventive step (MPEP 2144.04; In re Kuhle). Iterative use of the second dimension to clean up residuals flagged uncorrectable by the first dimension is the ordinary use of a product code.

4. Motivation to combine — summary for the record (KSR factors)

1. The applicant's own stated problem — bandwidth via serial/PCI‑Express links with integrity — supplies the design incentive (KSR factor: "market demand / design need").
2. Predictable variation: each added block (ECC, horizontal/diagonal ECC, redundant idle symbols, flag bits) performs exactly its known function.
3. Known technique to improve similar devices in the same way: PCIe, Fibre Channel, GigE and Xilinx transceivers already use 8B/10B + ordered sets + clock correction; adding FEC to that stack is the recognized next step.
4. "Obvious to try": the applicant enumerates a closed menu of interchangeable choices (4B5B / 8B10B / 64B66B; Hamming / Manchester / Reed‑Solomon; horizontal‑first / diagonal‑first), which is the hallmark of a finite set of identified, predictable solutions.

5. Anticipated patentee rebuttals and my assessment

• "Ordinary skill, not combination" — the strongest argument, and it cuts against patentability here (a claim whose elements were all known and combined by routine engineering is obvious).
• "Teaching away": US 2006/0176991 A1 (Nishimura; https://companyprofiles.justatic.com/patent/20060176991) states that "a coding system, such as the 8B10B coding system, that causes performance reduction is no longer necessary." That could be used against a combination requiring 8B/10B, but Widmer & Franaszek, PCIe, Fibre Channel and XAPP581 all affirmatively teach 8B/10B for CDR/DC balance, so the combination remains properly motivated.
• "Unexpected result": I see no evidence of record of unexpected results; the only asserted benefit (a lower uncorrectable‑error probability, ~10⁻⁴⁰) is a straightforward consequence of combining a horizontal and a diagonal code, i.e., precisely the expected benefit of a product code.
• Claim‑level caveat: I could not evaluate the dependent claims beyond claim 8 because the supplied text truncates there; if those claims recite specific register values, specific ECC polynomials, or the particular 20‑bit/5‑cycle transfer granularity, they should be analyzed separately for whether any such detail is non‑routine.

6. Bottom line

On the record available, claim 1 would have been obvious over PCI Express Base Specification in view of Widmer & Franaszek (8B/10B) and a conventional block ECC reference such as JP 2005‑512352 or standard Hamming/RS art. Claims 2–5 would have been obvious over that combination in further view of the PCIe/FC ordered‑set and clock‑correction art and Xilinx XAPP581. Claims 6–8 would have been obvious over Combination A in view of US 5,392,299 (Rhines) and/or JP 2005‑512352, with claim 7 versus claim 8 differing only in a decode order the applicant itself describes as interchangeable.

Confidence: Moderate‑to‑high on the legal framework and on the field‑level availability of each element; low on reference‑specific pinpoint citations, because I could not retrieve the actual USPTO "References Cited"/"Citations" list for US 8,103,942 B2 within this session. If you need an examiner‑grade chart, the next step is to pull the IFW file wrapper (USPTO PatentCenter for US 12/055,474 / US20080294966A1) and the JP5233165B2 examination record to obtain the exact cited documents and paragraphs.