Patent 7989944

Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

✓ Generated

To identify the most relevant prior art for US patent 7989944, I have examined each patent citation listed within the provided patent text. For each reference, I have extracted the full citation, publication/filing date, a brief description based on its title, and assessed its potential anticipation of the independent claims (Claim 1, Claim 15, and Claim 32) of US7989944 under 35 U.S.C. § 102. The earliest priority date for US7989944 is 2002-01-31, which serves as the critical date for prior art assessment.

Here is a detailed breakdown of each cited patent:

Citations to US Patent 7989944:

  1. US 4,246,595 A

    • Full Citation: US 4,246,595 A to Matsushita Electric Industrial Co., Ltd., published 1981-01-20.
    • Publication/Filing Date: Published: 1981-01-20 (Priority: 1977-03-08).
    • Brief Description: This patent describes an electronic circuit device and its manufacturing method, broadly focused on reducing size and improving reliability, potentially through component integration.
    • Potential Anticipation (35 U.S.C. § 102): Potentially anticipates the general concept of embedding components in a base for electrical devices. It could broadly cover elements of Claim 1 (insulating material layer, component inside, conductive patterns) and Claim 32 (microcircuit inside a hole), but is unlikely to disclose the specific hardened insulating polymer layer and contact opening details of US7989944.

  2. US 5,102,829 A

    • Full Citation: US 5,102,829 A to AT&T Bell Laboratories, published 1992-04-07.
    • Publication/Filing Date: Published: 1992-04-07 (Priority: 1991-07-22).
    • Brief Description: Describes a plastic pin grid array package, primarily concerning the packaging and interconnection of integrated circuits.
    • Potential Anticipation (35 U.S.C. § 102): Less likely to directly anticipate the independent claims of US7989944, as its focus is on component packaging rather than direct embedding within a circuit board's base material.

  3. US 5,162,613 A

    • Full Citation: US 5,162,613 A to AT&T Bell Laboratories, published 1992-11-10.
    • Publication/Filing Date: Published: 1992-11-10 (Priority: 1991-07-01).
    • Brief Description: Focuses on integrated circuit interconnection techniques, which may involve various substrate or packaging methods.
    • Potential Anticipation (35 U.S.C. § 102): Broadly covers interconnection and conductive patterns (relevant to Claim 1, 15, 32), but likely lacks the specific embedding structure and the distinct hardened polymer layer of US7989944.

  4. US 5,208,188 A

    • Full Citation: US 5,208,188 A to Advanced Micro Devices, Inc., published 1993-05-04.
    • Publication/Filing Date: Published: 1993-05-04 (Priority: 1989-10-02).
    • Brief Description: Details a process for multilayer lead frame assembly for IC structures and the resulting package.
    • Potential Anticipation (35 U.S.C. § 102): Focuses on "lead frame assembly" and "package," which is conceptually distinct from directly embedding unpackaged components into a circuit board's insulating material. It might share high-level concepts of multi-layer structures (Claim 15) but is unlikely to anticipate the specific embedding and interconnection details.

  5. US 5,216,806 A

    • Full Citation: US 5,216,806 A to Atmel Corporation, published 1993-06-08.
    • Publication/Filing Date: Published: 1993-06-08 (Priority: 1992-09-01).
    • Brief Description: Describes a method for forming a chip package and its interconnects.
    • Potential Anticipation (35 U.S.C. § 102): Similar to previous packaging patents, this is less likely to anticipate the specific embedding structure and hardened polymer layer within a circuit board base as claimed in US7989944.

  6. US 5,227,338 A

    • Full Citation: US 5,227,338 A to International Business Machines Corporation, published 1993-07-13.
    • Publication/Filing Date: Published: 1993-07-13 (Priority: 1990-04-30).
    • Brief Description: Describes a three-dimensional memory card structure with internal direct chip attachment. This is highly relevant due to "internal direct chip attachment" and "three-dimensional structure."
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant. Could potentially anticipate elements of Claim 1 (component inside insulating layer, conductive patterns), Claim 15 (multi-layered structure, embedded components), and Claim 32 (microcircuit inside, conductive patterns). The "direct chip attachment" is a key similarity to the "unpacked microcircuits" of US7989944.

  7. US 5,248,852 A

    • Full Citation: US 5,248,852 A to Matsushita Electric Industrial Co., Ltd., published 1993-09-28.
    • Publication/Filing Date: Published: 1993-09-28 (Priority: 1989-10-20).
    • Brief Description: Describes a resin circuit substrate and its manufacturing method, possibly involving embedded components.
    • Potential Anticipation (35 U.S.C. § 102): Relevant to Claim 1 (insulating material layer, component inside) as it deals with resin substrates. The general concept of embedding components in a resin matrix could be covered.

  8. US 5,306,670 A

    • Full Citation: US 5,306,670 A to Texas Instruments Incorporated, published 1994-04-26.
    • Publication/Filing Date: Published: 1994-04-26 (Priority: 1993-02-09).
    • Brief Description: Describes a multi-chip integrated circuit module and its fabrication method.
    • Potential Anticipation (35 U.S.C. § 102): Relevant to multi-chip integration (Claim 15). It could anticipate the general idea of embedding multiple components and forming electrical connections within a module.

  9. US 5,497,033 A

    • Full Citation: US 5,497,033 A to Martin Marietta Corporation, published 1996-03-05.
    • Publication/Filing Date: Published: 1996-03-05 (Priority: 1993-02-08).
    • Brief Description: Explicitly describes an "embedded substrate for integrated circuit modules."
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant to Claim 1 and Claim 32, directly addressing embedding components in a substrate. The terminology is very close to the core concept of US7989944.

  10. US 5,637,919 A

    • Full Citation: US 5,637,919 A to Grabbe; Dimitry G., published 1997-06-10.
    • Publication/Filing Date: Published: 1997-06-10 (Priority: 1993-07-28).
    • Brief Description: Focuses on a "perimeter independent precision locating member," suggesting methods for precise alignment or positioning of components.
    • Potential Anticipation (35 U.S.C. § 102): This patent might address alignment aspects (a step in US7989944's method) but is unlikely to anticipate the overall structural claims of US7989944.

  11. US 5,943,216 A

    • Full Citation: US 5,943,216 A to Photo Opto Electronic Technologies, published 1999-08-24.
    • Publication/Filing Date: Published: 1999-08-24 (Priority: 1997-06-03).
    • Brief Description: Describes an apparatus for a circuit board featuring two-sided, cavity-mounted, inverted components, implying component embedding in cavities.
    • Potential Anticipation (35 U.S.C. § 102): Relevant to Claim 1 and Claim 32 due to "cavity" and "mounted component circuit board." The concept of a component within a hole/cavity is similar.

  12. US 5,970,321 A

    • Full Citation: US 5,970,321 A to LSI Logic Corporation, published 1999-10-19.
    • Publication/Filing Date: Published: 1999-10-19 (Priority: 1996-01-31).
    • Brief Description: Describes a method for fabricating a microelectronic package with polymer ESD protection.
    • Potential Anticipation (35 U.S.C. § 102): Less direct anticipation of US7989944's core embedding structure, as it focuses on component packaging and ESD protection rather than embedding raw components into a circuit board base.

  13. US 6,015,722 A

    • Full Citation: US 6,015,722 A to Gore Enterprise Holdings, Inc., published 2000-01-18.
    • Publication/Filing Date: Published: 2000-01-18 (Priority: 1997-10-14).
    • Brief Description: Details a method for assembling an IC chip package using an underfill material, typically associated with flip-chip technology.
    • Potential Anticipation (35 U.S.C. § 102): Describes a technique (flip-chip with underfill) that US7989944 explicitly contrasts its invention with. While it deals with chip-to-substrate connection, the embedding approach of US7989944 is different.

  14. US 6,038,133 A

    • Full Citation: US 6,038,133 A to Matsushita Electric Industrial Co., Ltd., published 2000-03-14.
    • Publication/Filing Date: Published: 2000-03-14 (Priority: 1997-11-25).
    • Brief Description: Describes a "circuit component built-in module" and its production method, strongly suggesting embedded components.
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant to Claim 1, 15, and 32 due to the "built-in module" and embedding concept. This could potentially anticipate many aspects of embedding components and their interconnection within a substrate.

  15. US 6,100,108 A

    • Full Citation: US 6,100,108 A to Denso Corporation, published 2000-08-08.
    • Publication/Filing Date: Published: 2000-08-08 (Priority: 1997-02-17).
    • Brief Description: A general method of fabricating electronic circuit devices, potentially covering various integration techniques.
    • Potential Anticipation (35 U.S.C. § 102): Broad title. Unlikely to disclose the specific embedded component structure of US7989944 without further details.

  16. US 6,131,269 A

    • Full Citation: US 6,131,269 A to TRW Inc., published 2000-10-17.
    • Publication/Filing Date: Published: 2000-10-17 (Priority: 1998-05-18).
    • Brief Description: Focuses on circuit isolation techniques for RF and millimeter-wave modules, potentially involving shielding or special substrate designs.
    • Potential Anticipation (35 U.S.C. § 102): Relevant to the EMI shielding aspect of Claim 32 (metal foil covering sidewalls, metal plates forming shield, electrically connected to earth). This could potentially anticipate the general shielding structure around embedded components.

  17. US 6,154,366 A

    • Full Citation: US 6,154,366 A to Intel Corporation, published 2000-11-28.
    • Publication/Filing Date: Published: 2000-11-28 (Priority: 1999-11-23).
    • Brief Description: Describes moisture-resistant chip-on-flex packages, related to flexible circuits and chip integration.
    • Potential Anticipation (35 U.S.C. § 102): Mentions "chip-on-flex," which relates to flexible circuit boards (a preferred embodiment of US7989944). However, it pertains to "packages" rather than embedding directly into the base structure with the specific claimed layers.

  18. US 6,271,469 B1

    • Full Citation: US 6,271,469 B1 to Intel Corporation, published 2001-08-07.
    • Publication/Filing Date: Published: 2001-08-07 (Priority: 1999-11-12).
    • Brief Description: Describes building up layers directly on an encapsulated die package.
    • Potential Anticipation (35 U.S.C. § 102): Focuses on "encapsulated die package," which is different from embedding an unpacked component directly into the insulating material layer of a circuit board, as emphasized in US7989944.

  19. US 6,284,564 B1

    • Full Citation: US 6,284,564 B1 to Lockheed Martin Corp., published 2001-09-04.
    • Publication/Filing Date: Published: 2001-09-04 (Priority: 1999-09-20).
    • Brief Description: Describes a High-Density Interconnect (HDI) chip attachment method aiming for reduced processing.
    • Potential Anticipation (35 U.S.C. § 102): Relevant to the general goal of efficient chip attachment and interconnects. It could broadly relate to the manufacturing processes that result in structures covered by US7989944's claims.

  20. US 6,292,366 B1

    • Full Citation: US 6,292,366 B1 to Intel Corporation, published 2001-09-18.
    • Publication/Filing Date: Published: 2001-09-18 (Priority: 2000-06-26).
    • Brief Description: Explicitly describes a "Printed circuit board with embedded integrated circuit." This is highly relevant and directly on point with US7989944's core subject matter.
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant. Could potentially anticipate elements of Claim 1 (circuit board with embedded component, insulating material layer, conductive patterns), Claim 15 (if multi-layer), and Claim 32 (if it includes a microcircuit in a hole with sidewall metal and filler). This patent likely represents very close prior art.

  21. US 6,324,067 B1

    • Full Citation: US 6,324,067 B1 to Matsushita Electric Industrial Co., Ltd., published 2001-11-27.
    • Publication/Filing Date: Published: 2001-11-27 (Priority: 1995-11-16).
    • Brief Description: Describes a printed wiring board and its assembly.
    • Potential Anticipation (35 U.S.C. § 102): Broad title. Without further details, it's difficult to assess specific anticipation of US7989944's detailed embedding structure.

  22. US 2001/0054758 A1

    • Full Citation: US 2001/0054758 A1 to Isaak Harlan R., published 2001-12-27.
    • Publication/Filing Date: Published: 2001-12-27 (Priority: 2000-06-21).
    • Brief Description: Describes three-dimensional memory stacking using anisotropic epoxy interconnections, relating to multi-layer component integration.
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant to Claim 15 (multi-layered structure with embedded components). It directly mentions "three-dimensional memory stacking" and "epoxy interconnections," which are significant to US7989944's multi-layer embodiments and use of epoxy.

  23. JP 2002-016327 A

    • Full Citation: JP 2002-016327 A to NGK Spark Plug Co. Ltd., published 2002-01-18.
    • Publication/Filing Date: Published: 2002-01-18 (Priority: 2000-04-24).
    • Brief Description: Describes a wiring board and its manufacturing method.
    • Potential Anticipation (35 U.S.C. § 102): Broad title. Similar to US6324067B1, detailed analysis would be needed to determine specific anticipation of US7989944's embedding structure.

  24. US 2002/0020898 A1

    • Full Citation: US 2002/0020898 A1 to Vu Quat T., published 2002-02-21.
    • Publication/Filing Date: Published: 2002-02-21 (Priority: 2000-08-16).
    • Brief Description: Describes microelectronic substrates with integrated devices, clearly indicating embedding or integrating components.
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant to Claim 1, 15, and 32 due to "integrated devices" within "microelectronic substrates." This is very close to the core concept of embedding components in a base.

  25. US 2002/0063342 A1

    • Full Citation: US 2002/0063342 A1 to Blackshear Edmund D., published 2002-05-30.
    • Publication/Filing Date: Published: 2002-05-30 (Priority: 1999-08-09).
    • Brief Description: Describes pre-bond encapsulation for area array chips and wafer-scale packages, focusing on packaging and protection.
    • Potential Anticipation (35 U.S.C. § 102): More focused on encapsulation of existing packages, rather than embedding raw components directly into a circuit board during its manufacture as in US7989944.

  26. US 2002/0117743 A1

    • Full Citation: US 2002/0117743 A1 to Matsushita Electric Industrial Co., Ltd., published 2002-08-29.
    • Publication/Filing Date: Published: 2002-08-29 (Priority: 2000-12-27).
    • Brief Description: Describes a "component built-in module" and its manufacturing method, similar to US6038133A.
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant. "Component built-in module" directly points to embedding components and could potentially anticipate elements of Claim 1, 15, and 32.

  27. US 2002/0127770 A1

    • Full Citation: US 2002/0127770 A1 to Venkateshwaran Vaiyapuri, published 2002-09-12.
    • Publication/Filing Date: Published: 2002-09-12 (Priority: 2001-03-09).
    • Brief Description: Describes a die support structure.
    • Potential Anticipation (35 U.S.C. § 102): Might address aspects of supporting an embedded component (e.g., filler material in Claim 32) but is unlikely to anticipate the entire structural claims of US7989944.

  28. US 2002/0132096 A1

    • Full Citation: US 2002/0132096 A1 to NGK Spark Plug Co., Ltd., published 2002-09-19.
    • Publication/Filing Date: Published: 2002-09-19 (Priority: 2000-12-25).
    • Brief Description: Describes a wiring board.
    • Potential Anticipation (35 U.S.C. § 102): Broad title. General anticipation of a circuit board (Claim 1, 15, 32 as a broad category) but not the specific embedding details without further analysis.

  29. US 6,475,877 B1

    • Full Citation: US 6,475,877 B1 to Matsushita Electric Industrial Co., Ltd., published 2002-11-05.
    • Publication/Filing Date: Published: 2002-11-05 (Priority: 1995-11-16).
    • Brief Description: Describes a printed wiring board and its assembly.
    • Potential Anticipation (35 U.S.C. § 102): Broad title, similar to US6324067B1. Likely not specific enough to anticipate the detailed embedding structure unless the full text reveals it.

  30. US 6,486,001 B1

    • Full Citation: US 6,486,001 B1 to Amkor Technology, Inc., published 2002-11-26.
    • Publication/Filing Date: Published: 2002-11-26 (Priority: 1999-04-16).
    • Brief Description: Explicitly describes an "embedded component substrate package."
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant to Claim 1, 15, and 32. The term "embedded component substrate" directly addresses the core innovation of US7989944.

  31. US 2002/0180053 A1

    • Full Citation: US 2002/0180053 A1 to Infineon Technologies AG, published 2002-12-05.
    • Publication/Filing Date: Published: 2002-12-05 (Priority: 2001-05-30).
    • Brief Description: Describes a method for manufacturing an electronic component and the resulting component.
    • Potential Anticipation (35 U.S.C. § 102): Broad title. Without specifics, it's hard to tell if it anticipates the embedding method and structure of US7989944.

  32. US 6,492,723 B1

    • Full Citation: US 6,492,723 B1 to Agere Systems Guardian Corp., published 2002-12-10.
    • Publication/Filing Date: Published: 2002-12-10 (Priority: 2000-09-08).
    • Brief Description: Explicitly describes a "Printed wiring board having an embedded electronic component and method of fabricating same." This is highly relevant.
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant. This patent is likely very close prior art and potentially anticipates most, if not all, elements of Claim 1, and potentially Claim 15 (if it discusses multi-layering) and Claim 32 (if it discusses microcircuits in holes with shielding/filler).

  33. US 2002/0190367 A1

    • Full Citation: US 2002/0190367 A1 to International Business Machines Corporation, published 2002-12-19.
    • Publication/Filing Date: Published: 2002-12-19 (Priority: 2001-06-15).
    • Brief Description: Describes semiconductor packaging with integrated ground/power planes, relevant to power distribution and potential shielding.
    • Potential Anticipation (35 U.S.C. § 102): Relevant to the concept of conductive pattern layers defining metal plates (Claim 1) and their potential use as ground/power planes, which can also contribute to EMI shielding (Claim 32).

  34. US 6,518,648 B1

    • Full Citation: US 6,518,648 B1 to Intel Corporation, published 2003-02-11.
    • Publication/Filing Date: Published: 2003-02-11 (Priority: 2001-06-12).
    • Brief Description: Describes a microelectronic module with internal electronic components, directly indicating embedding components.
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant to Claim 1, 15, and 32 due to "internal electronic components." This is another strong piece of prior art.

  35. US 6,544,810 B1

    • Full Citation: US 6,544,810 B1 to Intel Corporation, published 2003-04-08.
    • Publication/Filing Date: Published: 2003-04-08 (Priority: 2000-06-05).
    • Brief Description: Describes a multi-chip module with through-package interconnects.
    • Potential Anticipation (35 U.S.C. § 102): Relevant to multi-chip modules (Claim 15) and through-package interconnects (conductors in contact openings, feed-throughs). This is strong prior art for the multi-layer and interconnection aspects.

  36. US 2003/0075806 A1

    • Full Citation: US 2003/0075806 A1 to Siemens Aktiengesellschaft, published 2003-04-24.
    • Publication/Filing Date: Published: 2003-04-24 (Priority: 2001-10-22).
    • Brief Description: Describes an electrical module and its production method.
    • Potential Anticipation (35 U.S.C. § 102): Broad title, similar to other general module patents. More detail would be needed to assess specific anticipation of US7989944's unique structural features.

  37. US 6,570,248 B2

    • Full Citation: US 6,570,248 B2 to Agere Systems Guardian Corp., published 2003-05-27.
    • Publication/Filing Date: Published: 2003-05-27 (Priority: 2000-09-08).
    • Brief Description: Identical title to US6492723B1, explicitly describing a "Printed wiring board having an embedded electronic component and method of fabricating same."
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant, identical to US6492723B1. This is very strong prior art for the embedding concept of US7989944.

  38. US 6,583,000 B1

    • Full Citation: US 6,583,000 B1 to Semiconductor Technology Research Center, published 2003-06-24.
    • Publication/Filing Date: Published: 2003-06-24 (Priority: 2000-09-29).
    • Brief Description: Describes a multi-layer interconnection substrate and its fabrication.
    • Potential Anticipation (35 U.S.C. § 102): Relevant to multi-layer aspects (Claim 15) and interconnection (Claim 1, 15, 32). Could potentially anticipate the general construction of stacked layers and interconnections.

  39. US 6,589,814 B1

    • Full Citation: US 6,589,814 B1 to Imbera Electronics Oy, published 2003-07-08.
    • Publication/Filing Date: Published: 2003-07-08 (Priority: 2002-01-31).
    • Brief Description: Describes an electronic module. This patent shares the same original assignee (Imbera Electronics Oy) and priority date (2002-01-31) as US7989944, indicating it is part of the same patent family.
    • Potential Anticipation (35 U.S.C. § 102): As this patent is part of the same patent family and shares the same priority date, it is generally not considered anticipatory prior art against US7989944 for common subject matter under 35 U.S.C. § 102, due to common inventorship/ownership and claiming priority. It represents a parallel or earlier granted patent within the same inventive effort.

  40. US 6,590,280 B2

    • Full Citation: US 6,590,280 B2 to General Electric Company, published 2003-07-08.
    • Publication/Filing Date: Published: 2003-07-08 (Priority: 2000-08-01).
    • Brief Description: Describes a "circuit board with integrated device and method of manufacture." This is highly relevant.
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant. This patent directly addresses a circuit board with an integrated (embedded) device. It could potentially anticipate Claim 1, 15, and 32, depending on the specifics of its structure, particularly the insulating layers, conductive patterns, and contact formation.

  41. US 6,600,223 B2

    • Full Citation: US 6,600,223 B2 to Intel Corporation, published 2003-07-29.
    • Publication/Filing Date: Published: 2003-07-29 (Priority: 2001-07-16).
    • Brief Description: Describes a "method of forming an integrated circuit package having an embedded device."
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant. Directly relates to embedding devices. Could potentially anticipate elements of Claim 1, 15, and 32, especially regarding the overall concept of embedding and the resulting structure.

  42. US 2003/0141617 A1

    • Full Citation: US 2003/0141617 A1 to Imbera Electronics Oy, published 2003-07-31.
    • Publication/Filing Date: Published: 2003-07-31 (Priority: 2002-01-31).
    • Brief Description: This patent application has an identical title and same original assignee (Imbera Electronics Oy) and same priority date (2002-01-31) as US7989944. The description of US7989944 states it is a continuation of application Ser. No. 10/502,336, which is associated with this publication.
    • Potential Anticipation (35 U.S.C. § 102): This is the parent application (US10/502,336) of US7989944. As such, it is not prior art in the anticipatory sense for its child/continuation, US7989944, as US7989944 claims priority to it. It is foundational to the patent family.

  43. US 6,610,550 B1

    • Full Citation: US 6,610,550 B1 to Freescale Semiconductor, Inc., published 2003-08-26.
    • Publication/Filing Date: Published: 2003-08-26 (Priority: 2000-09-27).
    • Brief Description: Describes a "wafer level package with embedded components and methods of forming same."
    • Potential Anticipation (35 U.S.C. § 102): Highly relevant. "Embedded components" at the "wafer level" could represent very close prior art to embedding chips in a base. This patent would require detailed comparison to ascertain if it anticipates the specific structural features of US7989944's independent claims.

  44. US 2003/0162335 A1

    • Full Citation: US 2003/0162335 A1 to Imbera Electronics Oy, published 2003-08-28.
    • Publication/Filing Date: Published: 2003-08-28 (Priority: 2002-01-31).
    • Brief Description: Describes an "electric module." Shares the same original assignee and priority date as US7989944, indicating it is likely part of the same patent family.
    • Potential Anticipation (35 U.S.C. § 102): Similar to US6589814B1 and US2003/0141617 A1, this is part of the same patent family and shares the same priority date. It is generally not considered anticipatory prior art against US7989944 for common subject matter under 35 U.S.C. § 102.

  45. US 6,638,783 B1

    • Full Citation: US 6,638,783 B1 to International Business Machines Corporation, published 2003-10-28.
    • Publication/Filing Date: Published: 2003-10-28 (Priority: 2001-09-26).
    • Brief Description: Describes a "system and method for embedding and interconnecting a semiconductor chip in an organic substrate." This is extremely relevant to US7989944.
    • Potential Anticipation (35 U.S.C. § 102): Extremely relevant. This patent directly describes embedding and interconnecting chips in an organic substrate, which is a core feature of US7989944 (e.g., FR4 baseboard). This is a very strong candidate for anticipating elements of Claim 1, 15, and 32.

Summary of Most Relevant Prior Art (excluding self-citations from the same family):

The patents most likely to be highly relevant prior art, potentially anticipating elements of US7989944's independent claims (Claim 1, 15, 32), are those that explicitly discuss embedding or integrating unpackaged components into a substrate or circuit board, especially those that pre-date US7989944's priority date of 2002-01-31. Key examples include:

  • US 5,227,338 A (1993-07-13) - "Three-dimensional memory card structure with internal direct chip attachment."
  • US 5,497,033 A (1996-03-05) - "Embedded substrate for integrated circuit modules."
  • US 6,038,133 A (2000-03-14) - "Circuit component built-in module and method for producing the same."
  • US 6,292,366 B1 (2001-09-18) - "Printed circuit board with embedded integrated circuit."
  • US 2001/0054758 A1 (2001-12-27) - "Three-dimensional memory stacking using anisotropic epoxy interconnections."
  • US 2002/0020898 A1 (2002-02-21) - "Microelectronic substrates with integrated devices."
  • US 2002/0117743 A1 (2002-08-29) - "Component built-in module and method for producing the same."
  • US 6,486,001 B1 (2002-11-26) - "Embedded component substrate package."
  • US 6,492,723 B1 (2002-12-10) - "Printed wiring board having an embedded electronic component and method of fabricating same." (Also US 6,570,248 B2 with an identical title.)
  • US 6,518,648 B1 (2003-02-11) - "Microelectronic module with internal electronic components."
  • US 6,544,810 B1 (2003-04-08) - "Multi-chip module with through-package interconnects."
  • US 6,590,280 B2 (2003-07-08) - "Circuit board with integrated device and method of manufacture."
  • US 6,600,223 B2 (2003-07-29) - "Method of forming an integrated circuit package having an embedded device."
  • US 6,610,550 B1 (2003-08-26) - "Wafer level package with embedded components and methods of forming same."
  • US 6,638,783 B1 (2003-10-28) - "System and method for embedding and interconnecting a semiconductor chip in an organic substrate."

These patents would require a detailed claim-by-claim comparison to US7989944 to determine the full extent of their anticipatory effect under 35 U.S.C. § 102, particularly focusing on the specific features of US7989944's independent claims such as the "hardened insulating polymer layer between the first surface of the component and at least one conductive pattern of said at least one second conductive pattern layer, and contact openings in the hardened insulating polymer layer and conductors in the contact openings for forming electrical contacts." The EMI shielding aspect of Claim 32 might also find anticipation in patents like US6131269A and US20020190367A1.

Generated 5/19/2026, 12:49:49 PM