Patent 7989944

Derivative works

Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.

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Derivative works

Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.

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Defensive Disclosure Document for US Patent 7989944

Current Date: April 26, 2026

This Defensive Disclosure Document aims to establish prior art for various derivative improvements and applications related to US Patent 7989944, "Method for embedding a component in a base." The intent is to render future incremental advancements in this domain obvious or non-novel, thereby limiting the patentability of such developments by competitors. This document focuses on extrapolating the core inventive concepts of embedding electronic components within a base structure, particularly printed circuit boards (PCBs) and electronic modules, into diverse technological contexts and operational paradigms.

Derivatives of Independent Claim 1: Circuit Board

Claim 1: A circuit board comprising an insulating material layer having a first side and a second side, at least one first conductive pattern layer on the first side of the insulating material layer, at least one of the first conductive pattern layers defining a first metal plate, at least one second conductive pattern layer on the second side of the insulating material layer, at least one of the second conductive pattern layers defining a second metal plate, a component inside the insulating material layer and between the first and second metal plates, the component having a first surface facing towards the second metal plate, and contact areas on the first surface, a hardened insulating polymer layer between the first surface of the component and at least one conductive pattern of said at least one second conductive pattern layer, and contact openings in the hardened insulating polymer layer and conductors in the contact openings for forming electrical contacts between the contact areas of the component and the at least one second conductive pattern layer or layers.

1. Material & Component Substitution

Derivative 1.1: High-Frequency Dielectric Substitution

  • Enabling Description: The insulating material layer (1) is substituted with a Liquid Crystal Polymer (LCP) substrate, known for its low dielectric constant (Dk < 3.0) and low dissipation factor (Df < 0.003) across microwave and millimeter-wave frequencies (e.g., 20-100 GHz). The conductive pattern layers (e.g., 2, 4) are formed from thin-film sputtered copper or silver alloys to minimize skin effect losses. The hardened insulating polymer layer (7) is a thermosetting polyimide with controlled dielectric properties to maintain impedance matching for contact openings (13) which utilize plated copper via fills, ensuring signal integrity for embedded RF components (18) such as RF transceivers or antenna elements. The component is fluxless attached to the LCP, and the polymer is cured via UV light or low-temperature thermal cycle to prevent degradation of LCP.
  • Technical Terminology: Liquid Crystal Polymer (LCP), dielectric constant (Dk), dissipation factor (Df), millimeter-wave, skin effect, thermosetting polyimide, impedance matching, plated copper via fills, RF transceiver, UV curing.
graph TD
    A[LCP Substrate (Insulating Material)] --> B(Sputtered Cu/Ag Conductive Pattern 1 - First Metal Plate)
    A --> C(Sputtered Cu/Ag Conductive Pattern 2 - Second Metal Plate)
    A --> D(Embedded RF Transceiver Component)
    D --> E(Component First Surface Contact Areas)
    E --> F(Hardened Polyimide Layer)
    F --> G(Contact Openings with Plated Cu Vias)
    G --> C
    B -- Shielding/Grounding --> D
    C -- Signal/Power --> D

Derivative 1.2: Ceramic-Reinforced Composite Base

  • Enabling Description: The baseboard (1) is fabricated from a ceramic-reinforced epoxy composite (e.g., alumina-filled epoxy, such as Panasonic Megtron 6). This material offers superior thermal conductivity (e.g., 1-2 W/mK) and improved dimensional stability compared to standard FR4, crucial for high-power applications or environments with wide temperature excursions. Conductive patterns (e.g., 2, 4) are thick-film copper. The embedded component (18) is a power discrete device, such as a Silicon Carbide (SiC) MOSFET or Gallium Nitride (GaN) HEMT, placed in a precisely milled cavity. The filler material (10) consists of a thermally conductive, electrically insulating epoxy loaded with boron nitride or aluminum nitride particles (e.g., >5 W/mK). The hardened insulating polymer layer (7) is a benzocyclobutene (BCB) dielectric, chosen for its low moisture absorption and excellent adhesion to ceramic composites, with copper pillars forming the contacts (14) through laser-ablated openings (13).
  • Technical Terminology: Ceramic-reinforced epoxy composite, alumina-filled epoxy, Megtron 6, thermal conductivity, dimensional stability, thick-film copper, power discrete device, SiC MOSFET, GaN HEMT, milled cavity, thermally conductive epoxy, boron nitride, aluminum nitride, benzocyclobutene (BCB), laser-ablated openings, copper pillars.
graph TD
    A[Ceramic-Reinforced Epoxy Baseboard] --> B(Thick-Film Cu Pattern 1 - First Metal Plate)
    A --> C(Thick-Film Cu Pattern 2 - Second Metal Plate)
    A --> D(Milled Cavity)
    D --> E[SiC MOSFET Component]
    E --> F{Thermally Conductive Filler Material}
    F --> D
    E -- Contact Areas --> G(Hardened BCB Dielectric Layer)
    G --> H(Laser-Ablated Contact Openings)
    H --> I(Cu Pillars)
    I --> C
    B -- Thermal Plane --> E

Derivative 1.3: MEMS Sensor Integration with Graphene Conductors

  • Enabling Description: The component (18) is a micro-electromechanical system (MEMS) sensor (e.g., accelerometer, gyroscope, or pressure sensor) designed for compact integration. The conductive patterns (2, 4, 12) are formed using chemical vapor deposition (CVD) of graphene or ink-jet printing of silver nanowires on a flexible polyimide film serving as the insulating material layer (1). This enables ultra-fine line widths (e.g., <5 µm) and improved mechanical flexibility. The hardened insulating polymer layer (7) is a photoimageable dielectric (e.g., Ajinomoto ABF), allowing for precise definition of contact openings (13) at the nanoscale. Electrical contacts (14) are established using electroless nickel immersion gold (ENIG) over graphene or silver nanowire pads, providing robust interconnections to the MEMS's contact bumps.
  • Technical Terminology: MEMS sensor, accelerometer, gyroscope, pressure sensor, chemical vapor deposition (CVD) graphene, silver nanowires, flexible polyimide film, ultra-fine line widths, photoimageable dielectric (PID), Ajinomoto ABF, nanoscale contact openings, electroless nickel immersion gold (ENIG), contact bumps.
graph TD
    A[Flexible Polyimide Layer] --> B(CVD Graphene/Ag Nanowire Pattern 1 - First Metal Plate)
    A --> C(CVD Graphene/Ag Nanowire Pattern 2 - Second Metal Plate)
    A --> D(Embedded MEMS Sensor)
    D --> E(Component First Surface Contact Areas)
    E --> F(Hardened Photoimageable Dielectric)
    F --> G(Electroless Ni/Au Contact Openings)
    G --> C
    B -- Data/Control Lines --> D
    C -- Power/Ground --> D

2. Operational Parameter Expansion

Derivative 1.4: Cryogenic Operation with Superconducting Traces

  • Enabling Description: The circuit board (1) is engineered for operation at cryogenic temperatures (e.g., 4 K for quantum computing or infrared sensing applications). The insulating material layer (1) is a low-CTE (Coefficient of Thermal Expansion) ceramic-filled polytetrafluoroethylene (PTFE) composite. The conductive pattern layers (2, 4) and conductors (14) are deposited niobium (Nb) or yttrium barium copper oxide (YBCO) thin films, functioning as superconductors below their critical temperatures. The embedded component (18) is a Josephson junction array or a superconducting quantum interference device (SQUID). The hardened insulating polymer layer (7) is a spin-on glass (SOG) or parylene-N film, providing ultrathin, low-stress insulation. Contact openings (13) are plasma-etched, and the superconducting conductors (14) are grown via sputter deposition or pulsed laser deposition (PLD), ensuring minimal electrical resistance at operational temperatures.
  • Technical Terminology: Cryogenic temperatures, quantum computing, infrared sensing, low-CTE, PTFE composite, niobium (Nb), YBCO (Yttrium Barium Copper Oxide), thin films, superconductors, critical temperature, Josephson junction array, SQUID, spin-on glass (SOG), parylene-N, plasma-etched, sputter deposition, pulsed laser deposition (PLD).
graph TD
    A[Low-CTE PTFE Insulating Layer] --> B(Nb/YBCO Superconducting Pattern 1 - First Metal Plate)
    A --> C(Nb/YBCO Superconducting Pattern 2 - Second Metal Plate)
    A --> D(Embedded Josephson Junction/SQUID)
    D --> E(Component First Surface Contact Areas)
    E --> F(Hardened SOG/Parylene-N Layer)
    F --> G(Plasma-Etched Contact Openings)
    G --> H(Sputter/PLD Grown Nb/YBCO Conductors)
    H --> C
    B -- Quantum Interconnects --> D

Derivative 1.5: Industrial Scale High-Voltage Power Module

  • Enabling Description: The circuit board (1) is an industrial-scale power module designed for high voltage (e.g., 10 kV) and high current applications (e.g., 1000 A). The insulating material layer (1) is a thick (e.g., 5-10 mm) ceramic substrate, such as Al₂O₃ or AlN, for high dielectric strength and thermal dissipation. The conductive pattern layers (2, 4) are electroplated copper layers (e.g., 200-500 µm thick) capable of carrying substantial current. The embedded components (18) are bare die IGBTs or power diodes, arranged for efficient heat transfer. The hardened insulating polymer layer (7) is a high-temperature resistant silicone elastomer or polyether ether ketone (PEEK) film, chosen for its excellent electrical insulation properties and partial discharge resistance at high voltages. Contact openings (13) are formed via abrasive blasting, and conductors (14) are copper wire bonds or robust copper posts, directly welded or sintered to the component contact areas (e.g., using silver sintering paste).
  • Technical Terminology: Industrial-scale, high voltage, high current, ceramic substrate (Al₂O₃, AlN), dielectric strength, thermal dissipation, electroplated copper, IGBTs, power diodes, bare die, high-temperature resistant silicone elastomer, PEEK film, partial discharge resistance, abrasive blasting, copper wire bonds, copper posts, silver sintering paste.
graph TD
    A[Thick Ceramic Substrate] --> B(Electroplated Cu Pattern 1 - First Metal Plate)
    A --> C(Electroplated Cu Pattern 2 - Second Metal Plate)
    A --> D(Embedded Bare Die IGBT/Power Diode)
    D --> E(Component First Surface Contact Areas)
    E --> F(Hardened Silicone/PEEK Layer)
    F --> G(Abrasive Blasted Contact Openings)
    G --> H(Cu Wire Bonds/Posts)
    H --> C
    B -- High Current Path --> D
    C -- High Voltage Connection --> D

3. Cross-Domain Application

Derivative 1.6: Autonomous Underwater Vehicle (AUV) Control Module

  • Enabling Description: The circuit board (1) serves as a ruggedized control module for Autonomous Underwater Vehicles (AUVs), requiring high pressure and salinity resistance. The insulating material layer (1) is a fiber-reinforced thermoset resin (e.g., carbon fiber/epoxy composite) hermetically sealed, offering structural integrity and resistance to hydrostatic pressure (e.g., up to 600 bar). Conductive patterns (2, 4) are gold-plated copper for corrosion resistance. The embedded component (18) is a pressure sensor or sonar transducer ASIC. The hardened insulating polymer layer (7) is a chemically resistant poly-p-xylylene (Parylene C) coating, applied via vapor deposition, providing a conformal, pinhole-free dielectric barrier. Contact openings (13) are micro-drilled and sealed with inert, hydrophobic conductive epoxy for robust electrical connections (14) to the component.
  • Technical Terminology: Autonomous Underwater Vehicle (AUV), hydrostatic pressure, salinity resistance, fiber-reinforced thermoset resin, carbon fiber/epoxy composite, hermetically sealed, gold-plated copper, corrosion resistance, pressure sensor, sonar transducer ASIC, Parylene C coating, vapor deposition, conformal coating, pinhole-free, micro-drilled, hydrophobic conductive epoxy.
graph TD
    A[Carbon Fiber/Epoxy Insulating Layer] --> B(Gold-Plated Cu Pattern 1 - First Metal Plate)
    A --> C(Gold-Plated Cu Pattern 2 - Second Metal Plate)
    A --> D(Embedded Pressure Sensor/Sonar ASIC)
    D --> E(Component First Surface Contact Areas)
    E --> F(Hardened Parylene C Coating)
    F --> G(Micro-Drilled & Epoxy Sealed Contact Openings)
    G --> H(Hydrophobic Conductive Epoxy Conductors)
    H --> C
    B -- Sensor Data Lines --> D

Derivative 1.7: Smart Agricultural Sensor Node

  • Enabling Description: The circuit board (1) functions as an embedded sensor node for smart agriculture, requiring robust operation in harsh outdoor environments (e.g., extreme temperatures, humidity, UV exposure). The insulating material layer (1) is a UV-stabilized liquid crystal polymer (LCP) or a specialized FR-4 variant with enhanced moisture resistance. The conductive patterns (2, 4) are thick-film printed silver or copper-nickel alloys for improved durability against environmental factors. The embedded component (18) is a soil moisture sensor or a multispectral imaging chip. The hardened insulating polymer layer (7) is a UV-curable acrylate or silicone-based encapsulant, providing a resilient barrier. Contact openings (13) are created via laser ablation, and the conductors (14) are plated with a robust tin-silver-copper (SAC) alloy, offering corrosion resistance and long-term reliability for connections to external communication modules.
  • Technical Terminology: Smart agriculture, sensor node, UV-stabilized LCP, FR-4 variant, moisture resistance, thick-film printed silver, copper-nickel alloys, soil moisture sensor, multispectral imaging chip, UV-curable acrylate, silicone-based encapsulant, laser ablation, tin-silver-copper (SAC) alloy, corrosion resistance.
graph TD
    A[UV-Stabilized LCP/FR-4 Insulating Layer] --> B(Thick-Film Ag/CuNi Pattern 1 - First Metal Plate)
    A --> C(Thick-Film Ag/CuNi Pattern 2 - Second Metal Plate)
    A --> D(Embedded Soil Moisture/Multispectral Chip)
    D --> E(Component First Surface Contact Areas)
    E --> F(Hardened UV-Curable Acrylate/Silicone)
    F --> G(Laser-Ablated Contact Openings)
    G --> H(SAC Alloy Plated Conductors)
    H --> C
    B -- Environmental Sensor Interface --> D

Derivative 1.8: Prosthetic Limb Control Unit

  • Enabling Description: The circuit board (1) forms the core of a prosthetic limb's neural control unit, demanding miniaturization, biocompatibility, and low power consumption. The insulating material layer (1) is a biocompatible polyimide or PEEK film, chosen for its flexibility and inertness. Conductive patterns (2, 4) are deposited platinum-iridium traces, known for their biocompatibility and corrosion resistance in biological environments. The embedded component (18) is a neural interface ASIC or a micro-controller unit (MCU) with low-power ARM cores. The hardened insulating polymer layer (7) is a medical-grade Parylene C coating, ensuring full encapsulation and tissue compatibility. Contact openings (13) are micromachined through the Parylene, and the conductors (14) are formed by anisotropic conductive film (ACF) bonding of platinum micro-wires or directly plated bio-compatible conductive polymers (e.g., PEDOT:PSS) for connection to neural electrodes.
  • Technical Terminology: Prosthetic limb, neural control unit, miniaturization, biocompatibility, low power consumption, polyimide, PEEK film, platinum-iridium traces, neural interface ASIC, micro-controller unit (MCU), ARM cores, medical-grade Parylene C, micromachined openings, anisotropic conductive film (ACF) bonding, platinum micro-wires, PEDOT:PSS, neural electrodes.
graph TD
    A[Biocompatible Polyimide/PEEK Layer] --> B(Pt-Ir Trace Pattern 1 - First Metal Plate)
    A --> C(Pt-Ir Trace Pattern 2 - Second Metal Plate)
    A --> D(Embedded Neural Interface ASIC/MCU)
    D --> E(Component First Surface Contact Areas)
    E --> F(Hardened Medical-Grade Parylene C)
    F --> G(Micromachined Contact Openings)
    G --> H(ACF Bonded Pt Micro-wires/PEDOT:PSS)
    H --> C
    B -- Neural Signal Acquisition --> D

4. Integration with Emerging Tech

Derivative 1.9: AI-Optimized Adaptive Circuit Board

  • Enabling Description: The fabrication process of the circuit board (1) is enhanced by an AI-driven optimization algorithm. This algorithm dynamically adjusts design parameters such as trace routing, via placement, and component thermal profiles based on real-time simulation data during the design phase. The insulating material layer (1) is a standard FR-4, but the component placement (18) and conductive patterns (2, 4) are iteratively optimized by the AI for minimal signal integrity degradation and optimal thermal management. The hardened insulating polymer layer (7) and contact openings (13) are manufactured with adaptive laser direct structuring (LDS) or inkjet printing techniques, where the manufacturing tool path is adjusted in real-time by the AI to compensate for material variations or process drift, thus maximizing yield and performance for embedded high-speed processors (e.g., FPGA, SoC). Embedded micro-sensors (e.g., thermistors, strain gauges) within the polymer layers (7, 11) provide feedback for continuous AI model refinement.
  • Technical Terminology: AI-driven optimization, trace routing, via placement, thermal profiles, real-time simulation, signal integrity, thermal management, adaptive laser direct structuring (LDS), inkjet printing, process drift, FPGA, SoC, embedded micro-sensors, thermistors, strain gauges, continuous AI model refinement.
graph TD
    A[AI Design Optimization Engine] --> B{Component Layout & Trace Routing}
    B --> C[FR-4 Insulating Material]
    C --> D(Embedded High-Speed FPGA/SoC)
    D --> E(Component Contact Areas)
    E --> F[Hardened Polymer Layer (Adaptive LDS/Inkjet)]
    F --> G(Contact Openings & Conductors)
    G --> H[Conductive Patterns (AI Optimized)]
    C -- Real-time Feedback from Embedded Sensors --> A
    A -- Adaptive Tool Path Adjustments --> F

Derivative 1.10: IoT-Enabled Self-Monitoring Circuit Board

  • Enabling Description: The circuit board (1) is integrated with a network of embedded IoT sensors for real-time monitoring of its operational health. Micro-temperature sensors, humidity sensors, and strain gauges (18) are embedded within the insulating material layer (1) (e.g., a flexible polyimide). These sensors communicate wirelessly (e.g., via NFC or ultra-low power Bluetooth Low Energy (BLE)) to an external gateway. The conductive pattern layers (2, 4) include embedded antennas for short-range wireless communication. The hardened insulating polymer layer (7) is a self-healing polymer (e.g., containing microcapsules of healing agents that release upon micro-crack formation) to enhance long-term reliability. Contact openings (13) lead to an embedded microcontroller (18) that aggregates sensor data and transmits health status. This microcontroller is connected via fine-pitch copper conductors (14) through the self-healing polymer layer.
  • Technical Terminology: IoT sensors, real-time monitoring, micro-temperature sensors, humidity sensors, strain gauges, flexible polyimide, NFC, Bluetooth Low Energy (BLE), embedded antennas, self-healing polymer, microcapsules, healing agents, micro-crack formation, embedded microcontroller, fine-pitch copper conductors.
graph TD
    subgraph IoT Sensor Network
        S1[Micro-Temp Sensor] --> M
        S2[Humidity Sensor] --> M
        S3[Strain Gauge] --> M
    end

    M[Embedded Microcontroller] --> A[Embedded Antenna (Conductive Pattern)]
    M -- Fine-Pitch Cu Conductors --> P[Self-Healing Polymer Layer]
    P -- Contact Openings --> M
    A -- Wireless Communication (NFC/BLE) --> G(External IoT Gateway)

    C[Insulating Material Layer (Flexible Polyimide)] -- Contains --> S1
    C -- Contains --> S2
    C -- Contains --> S3

Derivative 1.11: Blockchain-Verified Component Authenticity Board

  • Enabling Description: The circuit board (1) incorporates components (18) whose authenticity and supply chain provenance are verifiable via blockchain. Each embedded microcircuit (18) contains a unique physically unclonable function (PUF) or a secure element storing a cryptographic key. During the manufacturing process, a digital twin of the board is created on a blockchain. The insulating material layer (1) is a standard high-performance laminate. The hardened insulating polymer layer (7) contains embedded, optically verifiable micro-markers (e.g., quantum dots) whose pattern is unique to each manufacturing batch and recorded on the blockchain. Contact openings (13) lead to an embedded secure microcontroller that, upon power-up, queries the PUF and verifies its cryptographic signature against the blockchain record. The conductive patterns (2, 4) include dedicated, isolated security traces for this verification process, preventing external tampering.
  • Technical Terminology: Blockchain, supply chain provenance, physically unclonable function (PUF), secure element, cryptographic key, digital twin, optically verifiable micro-markers, quantum dots, manufacturing batch, secure microcontroller, cryptographic signature, isolated security traces.
graph TD
    subgraph Blockchain Network
        BCN[Blockchain Ledger]
    end

    C[Insulating Material Layer] --> M1[Embedded Secure Microcontroller]
    C --> M2[Embedded Microcircuit (with PUF)]

    M2 -- Query PUF/Key --> M1
    M1 -- Verify Signature --> BCN

    P[Hardened Polymer Layer (with Optically Verifiable Micro-markers)] -- Unique Pattern --> BCN
    P -- Contact Openings --> M1
    P -- Contact Openings --> M2

    L1[Conductive Pattern 1 (Security Traces)] --> M1
    L2[Conductive Pattern 2 (Power/Data)] --> M1
    L2 --> M2

    BCN -- Stores Digital Twin & Marker Data --> P

5. The "Inverse" or Failure Mode

Derivative 1.12: Safe-Failure Component Isolation Board

  • Enabling Description: The circuit board (1) is designed with a safe-failure mechanism for critical embedded components (18), such as power management ICs. The insulating material layer (1) incorporates fusible links or micro-switches adjacent to the embedded component. The hardened insulating polymer layer (7) is formulated with a thermally activated sacrificial layer that degrades and expands upon over-temperature events, creating a localized pressure increase. This pressure mechanically actuates the adjacent micro-switches or severs the fusible links in the conductive patterns (2, 4), isolating the faulty component from the rest of the circuit before cascading failure occurs. Conductors (14) are designed with a specific current-carrying capacity, ensuring the fusible links melt predictably. An embedded watchdog timer microcontroller monitors the component's health and initiates the safe-failure sequence if anomalous behavior is detected.
  • Technical Terminology: Safe-failure mechanism, fusible links, micro-switches, thermally activated sacrificial layer, over-temperature events, localized pressure, cascading failure, current-carrying capacity, watchdog timer microcontroller, anomalous behavior.
stateDiagram
    [*] --> Operational
    Operational --> OverTemperature: High Heat Detected
    Operational --> FaultDetected: Watchdog Timer
    OverTemperature --> SafeFailureInitiated: Polymer Degradation/Expansion
    FaultDetected --> SafeFailureInitiated: Watchdog Trip

    SafeFailureInitiated --> ComponentIsolation: Mechanical Actuation/Fusible Link Severed
    ComponentIsolation --> Isolated: Faulty Component Isolated
    Isolated --> [*]: System Safe

    state Operational {
        Subsystem1: Power Mgmt IC Active
        Subsystem2: Main Circuit Active
    }
    state SafeFailureInitiated {
        SystemStatus: Initiating Shutdown
    }

Derivative 1.13: Low-Power Standby Mode Circuit Board

  • Enabling Description: The circuit board (1) is optimized for a low-power standby mode, particularly for battery-powered or energy-harvesting applications. The embedded component (18) is a low-power microcontroller with multiple sleep states. The insulating material layer (1) is a thin, flexible polymer (e.g., PET or PEN) with embedded energy harvesting elements (e.g., thermoelectric generators or micro-PV cells). The conductive patterns (2, 4) are designed for dynamic voltage and frequency scaling (DVFS), with selective power gating implemented through fine-pitch traces (14) controlled by the embedded microcontroller. The hardened insulating polymer layer (7) has switchable dielectric properties (e.g., liquid crystal dielectric materials) that can be reconfigured to reduce parasitic capacitance and leakage currents when the board enters a low-power state. Contact openings (13) are equipped with micro-relays that disconnect non-essential circuitry in standby.
  • Technical Terminology: Low-power standby mode, battery-powered, energy-harvesting, low-power microcontroller, sleep states, flexible polymer (PET, PEN), thermoelectric generators, micro-PV cells, dynamic voltage and frequency scaling (DVFS), power gating, fine-pitch traces, switchable dielectric properties, parasitic capacitance, leakage currents, micro-relays.
graph TD
    A[Power Source (Battery/Energy Harvester)] --> B(Power Management Unit)
    B --> C{Micro-Relays for Power Gating}
    C --> D[Conductive Pattern 1 (DVFS Capable)]
    D --> E[Embedded Low-Power Microcontroller (Component)]
    E --> F[Hardened Polymer Layer (Switchable Dielectric)]
    F --> G(Contact Openings)
    G --> H[Conductive Pattern 2 (Data/Control)]
    E -- Controls Sleep States --> B
    E -- Controls DVFS/Power Gating --> C
    E -- Reconfigures Dielectric --> F
    H -- Connects To --> E
    J[Insulating Material Layer (with Energy Harvesters)] --> A

Derivative 1.14: Diagnostic Limited-Functionality Board

  • Enabling Description: The circuit board (1) includes an embedded component (18) which, upon detection of specific failure conditions or during debugging, can operate in a limited-functionality diagnostic mode. The insulating material layer (1) incorporates integrated self-test structures (e.g., boundary scan chains, loop-back paths). The conductive patterns (2, 4) include multiplexed diagnostic buses. The embedded component (18) is a complex ASIC or SoC that can reconfigure its internal logic (e.g., via eFuse or one-time programmable (OTP) memory) to disable non-essential blocks and activate diagnostic routines. The hardened insulating polymer layer (7) has specific, easily removable sacrificial sections over diagnostic test points (13), allowing for external probing in limited-functionality mode without damaging the primary circuit. Conductors (14) associated with these test points are robust, allowing for repeated connection/disconnection. An embedded bootloader manages the transition to and from diagnostic mode.
  • Technical Terminology: Diagnostic mode, limited-functionality, self-test structures, boundary scan chains, loop-back paths, multiplexed diagnostic buses, complex ASIC/SoC, eFuse, one-time programmable (OTP) memory, reconfigure internal logic, sacrificial sections, diagnostic test points, external probing, bootloader.
stateDiagram
    [*] --> FullOperationalMode
    FullOperationalMode --> ErrorDetected: System Error
    ErrorDetected --> DiagnosticMode: Initiates Diagnostic Bootloader
    FullOperationalMode --> DebuggingRequest: External Command

    DebuggingRequest --> DiagnosticMode
    DiagnosticMode --> SelfTestExecution: Runs Internal Diagnostics
    DiagnosticMode --> ExternalProbeAccess: Exposes Test Points
    SelfTestExecution --> ReportStatus: Sends Diagnostic Data
    ReportStatus --> FullOperationalMode: If Repairs Made/Error Cleared
    ExternalProbeAccess --> FullOperationalMode: If Debugging Complete

    state DiagnosticMode {
        Bootloader: Active
        NonEssentialBlocks: Disabled
        DiagnosticRoutines: Active
    }

Derivatives of Independent Claim 15: Multi-layered Circuit Board

Claim 15: A multi-layered circuit board comprising a first circuit board substructure and second circuit board substructure on top of each other, wherein at least the first circuit board substructure comprises an insulating material layer having a first side and a second side, at least one first conductive pattern layer on the first side of the insulating material layer, at least one of the conductive pattern layers defining a first metal plate, at least one second conductive pattern layer on the second side of the insulating material layer, at least one of the second conductive pattern layers defining a second metal plate, a component inside the insulating material layer and between the first and second metal plates, the component having a first surface facing towards the second metal plate, and contact areas on the first surface, a hardened insulating polymer layer between the first surface of the component and at least one conductive pattern of said at least one second conductive pattern layer, and contact openings in the hardened insulating polymer layer and conductors in the contact openings for forming electrical contacts between the contact areas of the component and the at least one second conductive pattern layer or layers.

1. Material & Component Substitution

Derivative 15.1: Heterogeneous Interlayer Dielectric Stacks

  • Enabling Description: The multi-layered circuit board utilizes a heterogeneous stack of interlayer dielectrics between substructures. For high-speed signal layers, a ceramic-filled liquid crystal polymer (LCP) prepreg is used, providing low Dk/Df properties. For power delivery layers, a thin layer of barium titanate (BaTiO₃) filled epoxy is employed for its high dielectric constant, enabling embedded decoupling capacitance. The first and second circuit board substructures each contain embedded components (e.g., high-speed memory in one, power management ICs in another). Vertical interconnects between substructures are formed by micro-via arrays filled with silver paste, followed by electrochemical copper plating, ensuring robust electrical and thermal paths. The embedded components are bare dies with through-silicon vias (TSVs) for efficient interconnection in a 3D fashion.
  • Technical Terminology: Heterogeneous stack, interlayer dielectrics, ceramic-filled LCP prepreg, low Dk/Df, barium titanate (BaTiO₃) filled epoxy, embedded decoupling capacitance, micro-via arrays, silver paste, electrochemical copper plating, bare dies, through-silicon vias (TSVs), 3D integration.
graph TD
    S1[First Substructure (LCP Dielectric)] -- Embedded High-Speed Memory --> P1(Power/Ground Plane)
    P1 -- Micro-via Array (Ag paste + Cu plate) --> IL1[BaTiO3-filled Epoxy (Decoupling)]
    IL1 -- Micro-via Array --> P2(High-Speed Signal Plane)
    P2 -- Micro-via Array --> IL2[LCP Prepreg (High-Speed)]
    IL2 -- Micro-via Array (Ag paste + Cu plate) --> S2[Second Substructure (Embedded Power IC)]

    S1 -- TSVs --> IL1
    S2 -- TSVs --> IL2

Derivative 15.2: Carbon Nanotube (CNT) Enhanced Vertical Interconnects

  • Enabling Description: In a multi-layered circuit board, the vertical electrical connections (e.g., inter-substructure vias) are fabricated using vertically aligned carbon nanotube (CNT) arrays, replacing traditional copper micro-vias. This provides superior electrical conductivity, enhanced thermal dissipation, and improved mechanical flexibility for boards subjected to bending stress. The insulating material layers within each substructure are flexible polyimide films. Components, such as flexible display drivers or bio-sensors, are embedded within these films. The hardened insulating polymer layers (7) are low-modulus silicone encapsulants. CNTs are grown directly within laser-drilled contact openings (13) between layers, then planarized and capped with a thin conductive adhesion layer for subsequent interconnection to the conductive patterns (2, 4) on each substructure. This allows for significantly higher aspect ratio vias and reduced signal latency.
  • Technical Terminology: Carbon nanotube (CNT) arrays, vertically aligned, micro-vias, electrical conductivity, thermal dissipation, mechanical flexibility, flexible polyimide films, flexible display drivers, bio-sensors, low-modulus silicone encapsulants, laser-drilled contact openings, planarized, adhesion layer, aspect ratio vias, signal latency.
graph TD
    S1[Flexible Polyimide Substructure 1] -- Embedded Display Driver --> C1(Conductive Pattern)
    C1 -- Laser-Drilled Opening --> CNT1[Vertically Aligned CNT Array]
    CNT1 -- Planarized/Capped --> C2(Conductive Pattern)
    C2 --> S2[Flexible Polyimide Substructure 2]
    S2 -- Embedded Bio-Sensor --> C3(Conductive Pattern)
    C3 -- Laser-Drilled Opening --> CNT2[Vertically Aligned CNT Array]
    CNT2 -- Planarized/Capped --> C4(Conductive Pattern)
    C4 --> S3[Flexible Polyimide Substructure 3]

    subgraph Hardened Polymer Layer (Silicone Encapsulant)
        HPL1[Layer 1] -- Covers --> S1
        HPL2[Layer 2] -- Covers --> S2
        HPL3[Layer 3] -- Covers --> S3
    end

2. Operational Parameter Expansion

Derivative 15.3: Ultra-High Density 3D Stacking with Micro-Bumps

  • Enabling Description: A multi-layered circuit board is configured for ultra-high density 3D integration, effectively creating a "PCB-based 3D IC" with multiple embedded bare die components. Each circuit board substructure is extremely thin (e.g., 50-100 µm total thickness) and contains different functional blocks (e.g., CPU, GPU, memory, specialized accelerators). The insulating material layer (1) in each substructure is a photosensitive organic dielectric (e.g., Ajinomoto ABF-GX). The embedded components (18) are ultra-thin silicon dies connected using fine-pitch (e.g., <20 µm) copper micro-bumps. The hardened insulating polymer layer (7) is precisely patterned to expose these micro-bumps, allowing for direct bonding of adjacent substructures. Inter-substructure connections are achieved via collective thermocompression bonding of these micro-bumps, forming a highly dense vertical interconnect fabric. The entire stack operates at significantly increased clock speeds due to reduced interconnect length and parasitics.
  • Technical Terminology: Ultra-high density 3D integration, PCB-based 3D IC, bare die, photosensitive organic dielectric, Ajinomoto ABF-GX, ultra-thin silicon dies, fine-pitch copper micro-bumps, hardened insulating polymer layer, thermocompression bonding, vertical interconnect fabric, clock speeds, interconnect length, parasitics.
graph TD
    subgraph Substructure A (50um)
        A1[Photosensitive Dielectric] -- Embedded CPU Die --> B1(Cu Micro-Bumps)
    end
    subgraph Substructure B (50um)
        A2[Photosensitive Dielectric] -- Embedded GPU Die --> B2(Cu Micro-Bumps)
    end
    subgraph Substructure C (50um)
        A3[Photosensitive Dielectric] -- Embedded Memory Die --> B3(Cu Micro-Bumps)
    end

    B1 -- Thermocompression Bonding --> B2
    B2 -- Thermocompression Bonding --> B3
    A1 -- Conductive Pattern --> B1
    A2 -- Conductive Pattern --> B2
    A3 -- Conductive Pattern --> B3

Derivative 15.4: Actively Cooled Multi-Layer Module for High Power

  • Enabling Description: This multi-layered circuit board is designed for extreme power density and actively cooled operation, suitable for server, data center, or electric vehicle inverter applications. The insulating material layers (1) in the substructures are ceramic substrates (e.g., AlN) chosen for high thermal conductivity. Embedded components (18) are high-power GaN/SiC power modules. Between specific circuit board substructures, dedicated microfluidic cooling channels (e.g., integrated into thin metal or polymer layers) are fabricated. These channels carry a dielectric coolant (e.g., fluorinert) to directly remove heat from the embedded components. The hardened insulating polymer layers (7) are high-temperature resistant, chemically inert epoxies. The contact openings (13) and conductors (14) are robust copper interconnects designed to withstand high current and temperature gradients, with a high aspect ratio for efficient heat transfer to the cooling layers.
  • Technical Terminology: Extreme power density, actively cooled operation, server, data center, electric vehicle inverter, ceramic substrates (AlN), high thermal conductivity, GaN/SiC power modules, microfluidic cooling channels, dielectric coolant (fluorinert), high-temperature resistant epoxy, high aspect ratio copper interconnects, temperature gradients.
graph TD
    S1[Substructure 1 (AlN, Embedded GaN Power Module)] --> C1(High-Current Cu Interconnects)
    C1 --> MCL1[Microfluidic Cooling Layer (Dielectric Coolant)]
    MCL1 --> S2[Substructure 2 (AlN, Embedded Control ASIC)]
    S2 --> C2(High-Current Cu Interconnects)
    C2 --> MCL2[Microfluidic Cooling Layer]
    MCL2 --> S3[Substructure 3 (AlN, Embedded Driver IC)]

    S1 -- Heat Transfer --> MCL1
    S2 -- Heat Transfer --> MCL1
    S2 -- Heat Transfer --> MCL2
    S3 -- Heat Transfer --> MCL2

3. Cross-Domain Application

Derivative 15.5: Secure Medical Device Implant with Redundancy

  • Enabling Description: A multi-layered circuit board functions as a secure, redundant control unit for medical implants (e.g., artificial pancreas, neurostimulator). Multiple identical circuit board substructures (e.g., two or three) are stacked, each containing a subset of critical components (18), such as a microcontroller, sensor interface, and communication module. The insulating material layers (1) are biocompatible polyimide films. The hardened insulating polymer layers (7) are medical-grade parylene-C coatings, ensuring hermeticity and biocompatibility. Logic for fault detection and switchover to redundant substructures is embedded within each microcontroller. Inter-substructure connections (14) utilize flexible platinum-iridium traces, allowing for slight conformational changes and providing highly reliable, biocompatible electrical paths. Power and data are multiplexed across redundant paths to enhance system reliability and prevent single points of failure.
  • Technical Terminology: Secure medical device implant, redundancy, artificial pancreas, neurostimulator, identical circuit board substructures, biocompatible polyimide films, medical-grade parylene-C coatings, hermeticity, fault detection, switchover, flexible platinum-iridium traces, conformational changes, multiplexed power/data.
graph TD
    subgraph Substructure A (Primary)
        MA[Microcontroller A] -- Controls --> SA[Sensor Interface A]
        MA -- Communicates --> CA[Comm Module A]
    end
    subgraph Substructure B (Redundant)
        MB[Microcontroller B] -- Controls --> SB[Sensor Interface B]
        MB -- Communicates --> CB[Comm Module B]
    end

    MA -- Flexible Pt-Ir Interconnect --> MB
    SA -- Flexible Pt-Ir Interconnect --> SB
    CA -- Flexible Pt-Ir Interconnect --> CB

    MA -- Fault Detection/Switchover Logic --> MB
    MB -- Fault Detection/Switchover Logic --> MA

    style MA fill:#f9f,stroke:#333,stroke-width:2px
    style MB fill:#ccf,stroke:#333,stroke-width:2px

Derivative 15.6: High-Reliability Automotive ADAS Module

  • Enabling Description: This multi-layered circuit board forms the core of an Advanced Driver-Assistance Systems (ADAS) module, demanding extreme reliability and operational robustness in automotive environments (e.g., shock, vibration, wide temperature range). The insulating material layers (1) are ceramic-filled polyimide or advanced thermoset composites. Components (18) such as radar processors, vision ASICs, and vehicle bus transceivers are embedded within different substructures. Inter-substructure connections are achieved via sinter-paste bonded copper posts for high thermal and mechanical reliability. The hardened insulating polymer layer (7) in each substructure is a low-stress, vibration-dampening epoxy underfill. The conductive patterns (2, 4) include dedicated ground and power planes to minimize electromagnetic interference (EMI) and ensure signal integrity for critical sensor data paths. A built-in self-test (BIST) logic is integrated into each embedded component, triggered at power-up and periodically during operation, to verify the integrity of the inter-layer connections and embedded components.
  • Technical Terminology: Advanced Driver-Assistance Systems (ADAS), extreme reliability, operational robustness, automotive environments, ceramic-filled polyimide, advanced thermoset composites, radar processors, vision ASICs, vehicle bus transceivers, sinter-paste bonded copper posts, thermal reliability, mechanical reliability, low-stress epoxy underfill, vibration-dampening, ground and power planes, EMI, signal integrity, built-in self-test (BIST), inter-layer connections.
graph TD
    S1[Substructure 1 (Embedded Radar Processor)] --> CuP1(Sinter-Paste Cu Posts)
    S2[Substructure 2 (Embedded Vision ASIC)] --> CuP2(Sinter-Paste Cu Posts)
    S3[Substructure 3 (Embedded Vehicle Bus Transceiver)]

    CuP1 -- Interconnect --> S2
    CuP2 -- Interconnect --> S3

    S1 -- Low-Stress Epoxy Underfill --> S1_HPL
    S2 -- Low-Stress Epoxy Underfill --> S2_HPL
    S3 -- Low-Stress Epoxy Underfill --> S3_HPL

    S1_HPL[HPL 1] -- Contact Openings --> S1
    S2_HPL[HPL 2] -- Contact Openings --> S2
    S3_HPL[HPL 3] -- Contact Openings --> S3

    S1 -- BIST --> S1_OK(Self-Test OK)
    S2 -- BIST --> S2_OK(Self-Test OK)
    S3 -- BIST --> S3_OK(Self-Test OK)

Derivative 15.7: High-Bandwidth Satellite Communication Array

  • Enabling Description: This multi-layered circuit board forms a module within a high-bandwidth satellite communication phased array antenna, operating at millimeter-wave frequencies (e.g., Ka-band, V-band). The individual circuit board substructures are ultra-thin (e.g., <50 µm) LCP or PTFE composite layers, each embedding a portion of the RF front-end (e.g., low-noise amplifiers, phase shifters, power amplifiers, antenna elements). The insulating material layers (1) are optimized for minimal loss at these frequencies. Vertical interconnects (14) between substructures are implemented using highly anisotropic conductive films (ACF) or non-conductive paste (NCP) with precisely aligned copper micro-bumps, minimizing reflections and insertion loss. The hardened insulating polymer layer (7) is a photoimageable benzocyclobutene (BCB) dielectric for precise patterning and integration of embedded passive elements (e.g., filters, couplers) between active RF components. The overall stack is designed for thermal management in vacuum conditions, possibly incorporating embedded thermal vias and radiating surfaces.
  • Technical Terminology: High-bandwidth, satellite communication, phased array antenna, millimeter-wave frequencies, Ka-band, V-band, ultra-thin LCP, PTFE composite, RF front-end, low-noise amplifiers (LNA), phase shifters, power amplifiers (PA), antenna elements, anisotropic conductive films (ACF), non-conductive paste (NCP), copper micro-bumps, reflections, insertion loss, photoimageable BCB, embedded passive elements, thermal management, vacuum conditions, embedded thermal vias.
graph TD
    S1[Substructure 1 (LNA + Phase Shifter)] --> MB1(Cu Micro-Bumps)
    S2[Substructure 2 (PA + Antenna Elements)] --> MB2(Cu Micro-Bumps)
    S3[Substructure 3 (Control ASIC)] --> MB3(Cu Micro-Bumps)

    MB1 -- ACF/NCP Bonding --> MB2
    MB2 -- ACF/NCP Bonding --> MB3

    S1 -- Embedded Passive Elements (BCB) --> S1_Active
    S2 -- Embedded Passive Elements (BCB) --> S2_Active
    S3 -- Embedded Passive Elements (BCB) --> S3_Active

    S1_Active[RF Component 1] --> S1
    S2_Active[RF Component 2] --> S2
    S3_Active[RF Component 3] --> S3

    subgraph Thermal Management
        TV[Thermal Vias] --> RadiatingSurface(Radiating Surface)
    end
    S1 -- Heat Dissipation --> TV
    S2 -- Heat Dissipation --> TV
    S3 -- Heat Dissipation --> TV

Derivatives of Independent Claim 32: Electronic Module

Claim 32: An electronic module comprising an insulating material layer having a first side and a second side, at least one first conductive pattern layer on the first side of the insulating material layer, at least one of the first conductive pattern layers defining a first metal plate, at least one second conductive pattern layer on the second side of the insulating material layer, at least one of the second conductive pattern layers defining a second metal plate, a hole having sidewalls defined in the insulating material layer and located between the first and second metal plates, a metal foil covering the sidewalls of the hole, a microcircuit inside the hole and having a first surface facing towards the second metal plate, and contact areas on the first surface, a filler material in the hole between the metal foil and the microcircuit, a hardened insulating polymer layer between the first surface of the microcircuit and at least one conductive pattern of said at least one second conductive pattern layer, and contact openings in the hardened insulating polymer layer and conductors in the contact openings for forming electrical contacts between the contact areas of the microcircuit and the at least one second conductive pattern layer or layers.

1. Material & Component Substitution

Derivative 32.1: Magnetic Shielding Module with Permalloy Foil

  • Enabling Description: The electronic module is designed for enhanced magnetic interference (MI) shielding. The metal foil covering the sidewalls of the hole (6) and defining the first and second metal plates (e.g., 2, 4) is substituted with a high-permeability permalloy (e.g., Mu-metal) foil, patterned via chemical etching. The microcircuit (18) embedded in the hole is a highly sensitive magnetic sensor (e.g., Hall effect sensor, magnetoresistive sensor). The insulating material layer (1) is a low-loss dielectric composite. The filler material (10) is a low-stress, non-magnetic epoxy. The hardened insulating polymer layer (7) is a thin polyimide film. Contact openings (13) and conductors (14) are standard copper, but all traces are carefully routed to minimize loops that could act as antennas for magnetic fields. The permalloy shield creates a quiescent magnetic environment for the sensor, improving signal-to-noise ratio.
  • Technical Terminology: Magnetic interference (MI) shielding, high-permeability permalloy, Mu-metal, chemical etching, magnetic sensor, Hall effect sensor, magnetoresistive sensor, low-loss dielectric composite, non-magnetic epoxy, polyimide film, quiescent magnetic environment, signal-to-noise ratio.
graph TD
    I[Insulating Material Layer] --> H(Hole with Sidewalls)
    H -- Covers --> P[Permalloy Foil (Sidewall & Metal Plates)]
    H -- Contains --> M[Magnetic Sensor Microcircuit]
    M --> F{Non-Magnetic Epoxy Filler}
    F --> P
    M -- Contact Areas --> PL[Hardened Polyimide Layer]
    PL --> CO[Contact Openings]
    CO --> CC[Copper Conductors]
    CC --> P

Derivative 32.2: Radiation-Hardened Module with Aerogel Filler

  • Enabling Description: The electronic module is designed for radiation-hardened applications (e.g., space, nuclear environments). The insulating material layer (1) is a radiation-resistant polyetherimide (PEI) or cyanate ester resin. The metal foil (e.g., 2, 4, sidewalls) is tungsten or tantalum for gamma ray shielding. The microcircuit (18) is a radiation-hardened ASIC. The filler material (10) is a silica aerogel or carbon aerogel composite, offering excellent shock absorption, low density, and thermal insulation while allowing for some radiation attenuation. The hardened insulating polymer layer (7) is a thin, radiation-crosslinked polyimide film. Contact openings (13) are laser-drilled, and the conductors (14) are gold-plated copper, designed for minimal material interactions under radiation exposure.
  • Technical Terminology: Radiation-hardened applications, space, nuclear environments, radiation-resistant polyetherimide (PEI), cyanate ester resin, tungsten, tantalum, gamma ray shielding, radiation-hardened ASIC, silica aerogel, carbon aerogel composite, shock absorption, thermal insulation, radiation attenuation, radiation-crosslinked polyimide film, laser-drilled, gold-plated copper.
graph TD
    I[Radiation-Resistant PEI/Cyanate Ester] --> H(Hole)
    H -- Covers --> T[Tungsten/Tantalum Foil (Shielding)]
    H -- Contains --> M[Radiation-Hardened ASIC]
    M --> F{Silica/Carbon Aerogel Filler}
    F --> T
    M -- Contact Areas --> PL[Hardened Radiation-Crosslinked Polyimide]
    PL --> CO[Contact Openings (Laser-Drilled)]
    CO --> GC[Gold-Plated Copper Conductors]
    GC --> T

2. Operational Parameter Expansion

Derivative 32.3: Ultra-Thin Single-Chip Module for Miniaturized Devices

  • Enabling Description: The electronic module is miniaturized to an ultra-thin single-chip package (e.g., <200 µm total thickness), suitable for smart cards or flexible wearables. The insulating material layer (1) is a flexible, ultra-thin (e.g., 25 µm) polyimide film. The hole (6) is micro-punched. The metal foil covering the sidewalls is eliminated or replaced by a very thin conductive seed layer for subsequent electroplating. The microcircuit (18) is a diced, ultra-thin silicon die (e.g., 30 µm thick). The filler material (10) is a low-viscosity, thermally curable liquid encapsulant, precisely dispensed to fill the micro-gap between the die and the flexible substrate. The hardened insulating polymer layer (7) is a photoimageable polybenzoxazole (PBO) for fine-pitch redistribution layer (RDL) formation. Contact openings (13) are formed by excimer laser ablation for fine-line pitch connections (e.g., <10 µm) with copper pillars (14).
  • Technical Terminology: Ultra-thin single-chip package, smart cards, flexible wearables, flexible polyimide film, micro-punched, conductive seed layer, electroplating, ultra-thin silicon die, low-viscosity liquid encapsulant, thermally curable, micro-gap, photoimageable polybenzoxazole (PBO), fine-pitch redistribution layer (RDL), excimer laser ablation, fine-line pitch connections, copper pillars.
graph TD
    I[Ultra-Thin Flexible Polyimide] --> H(Micro-Punched Hole)
    H -- Seed Layer/Electroplated Cu --> CW[Conductive Sidewalls (optional)]
    H -- Contains --> M[Ultra-Thin Silicon Die]
    M --> F{Low-Viscosity Liquid Encapsulant Filler}
    F --> CW
    M -- Contact Areas --> PL[Hardened Photoimageable PBO (RDL)]
    PL --> CO[Contact Openings (Excimer Laser)]
    CO --> CP[Copper Pillars]
    CP --> CPL1[Conductive Pattern Layer 1]
    CP --> CPL2[Conductive Pattern Layer 2]

Derivative 32.4: Extreme Environment Module with EMP Hardening

  • Enabling Description: This electronic module is engineered for extreme environments requiring electromagnetic pulse (EMP) hardening (e.g., military, critical infrastructure). The insulating material layer (1) is a high-Tg, radiation-hardened composite (e.g., polyimide-glass). The first and second metal plates (e.g., 2, 4) and the metal foil covering the sidewalls (6) form a continuous, hermetically sealed Faraday cage made of a highly conductive, thick copper-nickel alloy. The microcircuit (18) is an EMP-hardened processor. The filler material (10) is a conductive epoxy (e.g., silver-filled) providing both mechanical stability and additional shielding. All conductive paths (14) entering or leaving the Faraday cage are filtered with embedded EMI filters or transient voltage suppression (TVS) diodes within the hardened insulating polymer layer (7). The contact openings (13) are precisely drilled and plated through to ensure shield integrity. The entire module is designed to dissipate transient currents effectively through a robust grounding scheme connected to the shield.
  • Technical Terminology: Extreme environments, electromagnetic pulse (EMP) hardening, military, critical infrastructure, high-Tg, radiation-hardened composite, polyimide-glass, Faraday cage, hermetically sealed, copper-nickel alloy, EMP-hardened processor, conductive epoxy, silver-filled, EMI filters, transient voltage suppression (TVS) diodes, shield integrity, transient currents, robust grounding scheme.
graph TD
    I[High-Tg Radiation-Hardened Insulator] --> H(Hole)
    H -- Continuous --> FC[Faraday Cage (Cu-Ni Alloy)]
    FC -- Defines --> MP1(First Metal Plate)
    FC -- Defines --> MP2(Second Metal Plate)
    H -- Contains --> M[EMP-Hardened Processor Microcircuit]
    M --> F{Conductive Epoxy Filler}
    F --> FC
    M -- Contact Areas --> PL[Hardened Insulating Polymer Layer]
    PL --> CO[Contact Openings (Drilled & Plated)]
    CO --> CC[Conductors with EMI Filters/TVS Diodes]
    CC --> MP2
    FC -- Robust Grounding --> Ground(Earth Connection)

3. Cross-Domain Application

Derivative 32.5: Tamper-Evident Cryptographic Module for Secure Transactions

  • Enabling Description: This electronic module serves as a tamper-evident cryptographic module for secure financial transactions or digital rights management. The insulating material layer (1) is a multi-layered composite including sacrificial conductor layers and pressure sensors. The first and second metal plates (e.g., 2, 4) and the metal foil covering the sidewalls (6) form an electromagnetic shield with integrated tamper-detection meshes. The microcircuit (18) is a secure cryptographic processor with internal memory. The filler material (10) is a photosensitive resin that changes optical properties irreversibly upon exposure to UV light or X-rays, indicating attempted non-invasive inspection. The hardened insulating polymer layer (7) is a brittle, frangible glass-filled epoxy. Contact openings (13) are formed with micro-explosives (e.g., using laser-induced breakdown), creating complex, non-reproducible geometries. Conductors (14) are arranged in a "maze" pattern, making physical probing difficult. Any attempt to breach the shield or probe the conductors triggers an immediate self-destruct sequence, erasing cryptographic keys.
  • Technical Terminology: Tamper-evident, cryptographic module, secure financial transactions, digital rights management, sacrificial conductor layers, pressure sensors, electromagnetic shield, tamper-detection meshes, secure cryptographic processor, internal memory, photosensitive resin, irreversible optical properties, UV light, X-rays, non-invasive inspection, brittle, frangible glass-filled epoxy, micro-explosives, laser-induced breakdown, non-reproducible geometries, maze pattern, physical probing, self-destruct sequence, cryptographic keys.
stateDiagram
    [*] --> SecureOperatingMode
    SecureOperatingMode --> TamperDetected: Shield Breach | Pressure Sensor | Optical Change
    TamperDetected --> SelfDestructSequence: Initiate Key Erasure
    SelfDestructSequence --> Erased: Cryptographic Keys Erased
    Erased --> FailSafeMode: Module Enters Fail-Safe Mode
    FailSafeMode --> [*]

    state SecureOperatingMode {
        CryptoProcessor: Active
        TamperMeshes: Monitoring
        Resin: Untouched
    }

Derivative 32.6: Environmental Monitoring Capsule for Remote Sensing

  • Enabling Description: The electronic module is designed as an autonomous, long-duration environmental monitoring capsule for remote, inaccessible locations (e.g., deep sea, volcanic vents, arctic ice). The insulating material layer (1) is a specialized polymer-ceramic composite (e.g., PEEK-hydroxyapatite for bio-integration, or high-density polyethylene for extreme cold). The metal foil (sidewalls, metal plates 2, 4) is a titanium or Hastelloy alloy for corrosion resistance and structural integrity. The microcircuit (18) is an ultra-low-power environmental sensor array (e.g., pH, dissolved oxygen, methane, radiation). The filler material (10) is a pressure-compensating silicone gel, allowing the capsule to withstand extreme pressure changes. The hardened insulating polymer layer (7) is a self-cleaning, bio-fouling resistant coating (e.g., fluoropolymer or specialized ceramic coating). Contact openings (13) lead to robust, hermetically sealed connectors (14) for external probes or inductive charging, designed to maintain integrity over years in harsh conditions.
  • Technical Terminology: Autonomous, long-duration, environmental monitoring capsule, remote sensing, deep sea, volcanic vents, arctic ice, polymer-ceramic composite, PEEK-hydroxyapatite, high-density polyethylene, titanium, Hastelloy alloy, corrosion resistance, ultra-low-power environmental sensor array, pH, dissolved oxygen, methane, radiation, pressure-compensating silicone gel, bio-fouling resistant coating, fluoropolymer, ceramic coating, hermetically sealed connectors, inductive charging.
graph TD
    I[Specialized Polymer-Ceramic Insulator] --> H(Hole)
    H -- Titanium/Hastelloy Alloy --> FC[Corrosion-Resistant Casing/Plates]
    H -- Contains --> M[Ultra-Low-Power Sensor Array Microcircuit]
    M --> F{Pressure-Compensating Silicone Gel}
    F --> FC
    M -- Contact Areas --> PL[Hardened Self-Cleaning/Bio-fouling Resistant Coating]
    PL --> CO[Contact Openings]
    CO --> HC[Hermetically Sealed Connectors (Inductive Charging)]
    HC --> FC

Derivative 32.7: Drone-Mounted High-Resolution Imaging Module

  • Enabling Description: This electronic module is a lightweight, vibration-tolerant, high-resolution imaging module for drone applications. The insulating material layer (1) is a lightweight, high-modulus composite (e.g., carbon fiber-reinforced epoxy prepreg). The first and second metal plates (e.g., 2, 4) and the metal foil covering the sidewalls (6) are vapor-deposited aluminum or copper, designed for optimal thermal dissipation of the embedded imaging processor. The microcircuit (18) is a high-speed image signal processor (ISP) or an array of image sensors. The filler material (10) is a low-density, vibration-absorbing foam encapsulant (e.g., polyurethane foam). The hardened insulating polymer layer (7) is a transparent, optically clear dielectric (e.g., acrylic or cyclic olefin polymer) to allow light transmission to an embedded sensor's active surface. Contact openings (13) and conductors (14) are optimized for high-speed data transfer (e.g., MIPI CSI-2 interface) with impedance-controlled routing.
  • Technical Terminology: Drone applications, lightweight, vibration-tolerant, high-resolution imaging module, carbon fiber-reinforced epoxy prepreg, vapor-deposited aluminum/copper, thermal dissipation, high-speed image signal processor (ISP), image sensor array, low-density, vibration-absorbing foam encapsulant, polyurethane foam, transparent, optically clear dielectric, acrylic, cyclic olefin polymer, light transmission, MIPI CSI-2 interface, impedance-controlled routing.
graph TD
    I[Lightweight Carbon Fiber-Epoxy Insulator] --> H(Hole)
    H -- Vapor-Deposited Al/Cu --> TM[Thermal Dissipation/Shielding Metal]
    TM -- Defines --> MP1(First Metal Plate)
    TM -- Defines --> MP2(Second Metal Plate)
    H -- Contains --> M[High-Speed ISP/Image Sensor Array]
    M --> F{Vibration-Absorbing Foam Encapsulant}
    F --> TM
    M -- Active Surface --> TCD[Transparent, Optically Clear Dielectric Layer]
    M -- Contact Areas --> PL[Hardened Insulating Polymer Layer]
    PL --> CO[Contact Openings]
    CO --> HSCT[High-Speed Conductors (MIPI CSI-2)]
    HSCT --> MP2
    TCD -- Light Transmission --> M

4. Integration with Emerging Tech

Derivative 32.8: AI-Accelerated Smart Sensor Module

  • Enabling Description: This electronic module integrates an AI accelerator for on-device inferencing, acting as a smart sensor for real-time object detection or predictive maintenance. The insulating material layer (1) supports high-density integration. The first and second metal plates (e.g., 2, 4) and sidewall metal foil (6) form a robust thermal management and EMI shield. The microcircuit (18) is a dedicated AI accelerator (e.g., a neural processing unit, NPU) with integrated memory. The filler material (10) is a phase-change material (PCM) embedded for transient thermal buffering during peak AI processing loads. The hardened insulating polymer layer (7) includes embedded distributed temperature sensors that feed real-time thermal data to the NPU. The NPU dynamically adjusts its clock frequency and power consumption based on thermal conditions, optimizing performance within safe operating limits. Contact openings (13) and conductors (14) are high-bandwidth interconnects (e.g., chip-on-film (CoF) connections) to an external data bus.
  • Technical Terminology: AI accelerator, on-device inferencing, smart sensor, real-time object detection, predictive maintenance, high-density integration, thermal management, EMI shield, neural processing unit (NPU), phase-change material (PCM), transient thermal buffering, embedded distributed temperature sensors, clock frequency, power consumption, chip-on-film (CoF) connections, high-bandwidth interconnects.
graph TD
    I[Insulating Material Layer] --> H(Hole)
    H -- Thermal/EMI Shield --> TM[Metal Foil/Plates]
    H -- Contains --> M[AI Accelerator NPU]
    M --> F{Phase-Change Material Filler}
    F --> TM
    M -- Contact Areas --> PL[Hardened Polymer Layer (with Embedded Temp Sensors)]
    PL --> CO[Contact Openings]
    CO --> BWIC[High-Bandwidth Interconnects (CoF)]
    BWIC --> EB(External Data Bus)
    PL -- Real-time Thermal Data --> M
    M -- Dynamic Adjustment --> M

Derivative 32.9: IoT-Enabled Predictive Maintenance Module

  • Enabling Description: This electronic module is a robust, IoT-enabled predictive maintenance sensor for industrial machinery. The insulating material layer (1) is a rugged, high-Tg composite. The first and second metal plates (e.g., 2, 4) and sidewall metal foil (6) provide grounding and EMI protection. The microcircuit (18) is a multi-sensor SoC combining accelerometers, acoustic sensors, and environmental sensors, along with a low-power wireless transceiver (e.g., LoRa, NB-IoT). The filler material (10) is a viscoelastic polymer chosen for its dampening properties against industrial vibrations. The hardened insulating polymer layer (7) incorporates embedded micro-batteries or energy harvesting films (e.g., piezoelectric) to power the SoC. Contact openings (13) and conductors (14) connect to a miniaturized antenna embedded in the conductive pattern layer (2) for long-range wireless communication of diagnostic data to a cloud-based predictive analytics platform.
  • Technical Terminology: IoT-enabled, predictive maintenance, industrial machinery, rugged, high-Tg composite, EMI protection, multi-sensor SoC, accelerometers, acoustic sensors, environmental sensors, low-power wireless transceiver, LoRa, NB-IoT, viscoelastic polymer, dampening properties, industrial vibrations, embedded micro-batteries, energy harvesting films, piezoelectric, miniaturized antenna, long-range wireless communication, cloud-based predictive analytics.
graph TD
    I[Rugged High-Tg Insulator] --> H(Hole)
    H -- Grounding/EMI Shield --> GM[Metal Foil/Plates]
    H -- Contains --> M[Multi-Sensor SoC (IoT Component)]
    M --> F{Viscoelastic Polymer Filler}
    F --> GM
    M -- Contact Areas --> PL[Hardened Polymer Layer (with Micro-Batteries/Energy Harvesters)]
    PL --> CO[Contact Openings]
    CO --> M(SoC)
    PL -- Power --> M
    M -- Wireless Tx --> MA[Miniaturized Embedded Antenna]
    MA --> CP2[Conductive Pattern Layer 2]
    CP2 -- Long-Range Wireless Comm --> C(Cloud Predictive Analytics)

Derivative 32.10: Blockchain for Supply Chain Auditability Module

  • Enabling Description: This electronic module provides secure and auditable supply chain provenance for critical components, leveraging blockchain technology. The insulating material layer (1) is a specialized polymer with embedded unique identification markers (e.g., DNA taggants, cryptographic inks) detectable by external scanners. The first and second metal plates (e.g., 2, 4) and sidewall metal foil (6) are standard EMI shields. The microcircuit (18) is a secure microcontroller capable of generating and verifying cryptographic hashes. The filler material (10) contains a unique serialized particulate filler (e.g., micro-taggants) whose distribution pattern is recorded on a blockchain at the time of manufacture. The hardened insulating polymer layer (7) has a transparent window over the serialized filler, allowing for optical verification using an external imaging system. Contact openings (13) and conductors (14) connect the microcontroller to a secure communication interface, enabling it to query and update the blockchain ledger regarding component status (e.g., assembly dates, test results).
  • Technical Terminology: Blockchain, supply chain auditability, unique identification markers, DNA taggants, cryptographic inks, EMI shields, secure microcontroller, cryptographic hashes, serialized particulate filler, micro-taggants, distribution pattern, transparent window, optical verification, secure communication interface, blockchain ledger.
graph TD
    I[Insulating Material (with ID Markers)] --> H(Hole)
    H -- EMI Shield --> ESM[Metal Foil/Plates]
    H -- Contains --> M[Secure Microcontroller]
    M --> F{Serialized Particulate Filler}
    F --> ESM
    M -- Contact Areas --> PL[Hardened Polymer Layer (with Transparent Window)]
    PL --> CO[Contact Openings]
    CO --> SCI[Secure Communication Interface]
    SCI --> BLM[Blockchain Ledger Management]
    BLM --> BCN[Blockchain Network]
    PL -- Optical Verification --> ES(External Scanner)
    ES --> BCN
    M -- Query/Update --> BCN

5. The "Inverse" or Failure Mode

Derivative 32.11: Active Tamper-Responsive Data Erasure Module

  • Enabling Description: This electronic module is designed for active tamper response, specifically for immediate data erasure upon detecting a physical breach. The insulating material layer (1) incorporates integrated optical fiber loops and strain gauges. The first and second metal plates (e.g., 2, 4) and the metal foil covering the sidewalls (6) are part of a continuous, multi-layered tamper-detection mesh that forms an electrical circuit. The microcircuit (18) is a sensitive data processor with volatile memory (e.g., SRAM) and an embedded hardware security module (HSM) containing cryptographic keys. The filler material (10) is a fast-setting, electrically resistive epoxy. The hardened insulating polymer layer (7) has embedded micro-switches or "kill-wires" that are normally open. Any breach of the optical loops, strain gauges, or electrical mesh breaks the tamper-detection circuit, which is monitored by the HSM. Upon detection, the HSM immediately triggers a high-current pulse through the kill-wires, irreversibly destroying critical memory cells and erasing cryptographic keys within nanoseconds.
  • Technical Terminology: Active tamper response, data erasure, physical breach, optical fiber loops, strain gauges, multi-layered tamper-detection mesh, electrical circuit, sensitive data processor, volatile memory (SRAM), hardware security module (HSM), cryptographic keys, fast-setting, electrically resistive epoxy, embedded micro-switches, kill-wires, high-current pulse, irreversibly destroying memory cells, nanoseconds.
stateDiagram
    [*] --> SecureIdle
    SecureIdle --> DataProcessing: Request Received
    DataProcessing --> SecureIdle: Processing Complete

    state SecureIdle {
        HSM: Monitoring Sensors
        Memory: Intact
        KillWires: Dormant
    }
    state DataProcessing {
        CryptoEngine: Active
        Memory: Volatile Data
    }

    SecureIdle --> TamperDetected: Optical Loop Break | Strain Gauge Trip | Mesh Breach
    DataProcessing --> TamperDetected: Optical Loop Break | Strain Gauge Trip | Mesh Breach

    TamperDetected --> HighCurrentPulse: HSM Triggers Kill-Wires
    HighCurrentPulse --> MemoryDestruction: Critical Memory Cells Destroyed
    MemoryDestruction --> KeysErased: Cryptographic Keys Irretrievable
    KeysErased --> FailSafeState: Module Enters Fail-Safe Mode
    FailSafeState --> [*]

Derivative 32.12: Degraded Performance Mode Module with Shield Degradation Monitoring

  • Enabling Description: This electronic module operates in a degraded performance mode upon detection of electromagnetic shield degradation, common in high-stress applications. The insulating material layer (1) includes integrated micro-antennas and impedance sensors within its structure. The first and second metal plates (e.g., 2, 4) and the metal foil covering the sidewalls (6) are designed with a patterned impedance grid for continuous self-monitoring. The microcircuit (18) is an RF transceiver or high-speed data processor. The filler material (10) is a transparent, UV-fluorescent epoxy. The hardened insulating polymer layer (7) has a dedicated channel for a "shield integrity test signal" generated by the microcircuit. This signal is emitted and received by the integrated micro-antennas. Any change in the received signal's amplitude or phase (monitored by the microcircuit) indicates a degradation of the external shield. Upon detection, the microcircuit automatically reduces its clock frequency, power output, or switches to a lower-bandwidth, more robust communication protocol to minimize EMI emissions and susceptibility, entering a degraded performance mode.
  • Technical Terminology: Degraded performance mode, electromagnetic shield degradation, micro-antennas, impedance sensors, patterned impedance grid, self-monitoring, RF transceiver, high-speed data processor, transparent, UV-fluorescent epoxy, shield integrity test signal, signal's amplitude/phase, clock frequency reduction, power output reduction, lower-bandwidth communication protocol, EMI emissions, EMI susceptibility.
stateDiagram
    [*] --> FullPerformanceMode
    FullPerformanceMode --> ShieldDegradationDetected: Impedance Change | Signal Amplitude/Phase Drop
    ShieldDegradationDetected --> DegradedPerformanceMode: Microcircuit Adjusts Parameters
    DegradedPerformanceMode --> FullPerformanceMode: Shield Repaired / Conditions Improve

    state FullPerformanceMode {
        RFTransceiver: Max Clock Freq
        PowerOutput: High
        CommProtocol: High-Bandwidth
        Shield: Intact
    }
    state DegradedPerformanceMode {
        RFTransceiver: Reduced Clock Freq
        PowerOutput: Low
        CommProtocol: Low-Bandwidth/Robust
        Shield: Degraded
    }

Combination Prior Art Scenarios

Here are three combination prior art scenarios where US Patent 7989944's core concepts (embedding components, conductive patterns, insulating layers, contact formation) can be combined with existing open-source standards to demonstrate obviousness of further developments.

1. Combination with Open-Source Hardware Development Boards (e.g., Arduino/Raspberry Pi):

  • Scenario: An embedded component design methodology, as described in US7989944, is applied to manufacture a miniaturized, ruggedized version of an open-source development board (e.g., a variant of an Arduino Nano or a Raspberry Pi Zero W). Instead of surface-mounting components, the microcontroller (e.g., ATmega328P for Arduino, BCM2835 for Raspberry Pi) and essential passive components (resistors, capacitors) are embedded directly within the insulating material layer of a multi-layered PCB. The conductive patterns are designed to expose standard headers (e.g., 2.54mm pitch for GPIO, USB, power) compatible with the existing Arduino/Raspberry Pi ecosystems. The hardened insulating polymer layer and contact openings form direct, solderless connections to the embedded chips' pads. This combination makes the concept of highly integrated, embedded versions of popular open-source hardware platforms obvious, demonstrating how the patent's core embedding technique can be directly used to miniaturize and ruggedize existing, widely known open-source designs. The primary function (e.g., running Arduino sketches or Raspberry Pi OS) remains, but the form factor and environmental resilience are enhanced.
  • Relevant Open-Source Standard: Arduino Platform Specification (e.g., pinout, voltage levels, programming interface), Raspberry Pi Hardware Documentation (e.g., BCM pinout, dimensions, power requirements).

2. Combination with Open-Source EDA Tools (e.g., KiCad/gEDA) for Design Automation:

  • Scenario: The manufacturing process described in US7989944 (particularly the stages of hole making, conductive pattern formation, polymer film lamination, component placement, and contact formation) is entirely managed and optimized using an open-source Electronic Design Automation (EDA) software suite, such as KiCad or gEDA. The design files (schematics, PCB layouts) are generated in these open-source tools. A script (e.g., Python-based, utilizing KiCad's Python API) is developed to automatically generate the necessary machine instructions for laser drilling, CNC milling, pick-and-place machines, and electroplating based on the embedded component's footprint and desired interconnects. The design rules for embedded components, clearance, and via formation (as enabled by US7989944) are integrated into the open-source tool's design rule checker. This demonstrates that the design automation of embedded component PCBs, leveraging the techniques of US7989944, is an obvious extension using readily available open-source software, making the entire design-to-manufacture workflow for such boards readily achievable and transparent.
  • Relevant Open-Source Standard: KiCad File Format Specifications (e.g., .kicad_pcb, .sch), gEDA PCB Layout Format, Python APIs for EDA tools.

3. Combination with Open Standards for High-Speed Interconnects (e.g., MIPI, PCIe) for Embedded IP Cores:

  • Scenario: An electronic module (as per Claim 32) containing an embedded microcircuit (e.g., a CPU or GPU IP core) is designed to interface with other system components using an open standard high-speed interconnect protocol, such as MIPI (Mobile Industry Processor Interface) D-PHY/CSI-2/DSI or PCIe (PCI Express). The insulating material layer and conductive patterns within the module are optimized for impedance control and signal integrity required by these standards. The embedded microcircuit itself is a bare die implementing the PHY and controller layers of the chosen MIPI/PCIe standard. The hardened insulating polymer layer and its contact openings/conductors form the precise micro-scale connections to the embedded IP core's pads. These connections are routed to form a standard MIPI or PCIe connector interface on the exterior of the module, or directly to an adjacent embedded module via high-density interposers. This combination renders obvious the integration of widely adopted, high-speed open standard interfaces directly with embedded component technology, showing how such modules can be seamlessly incorporated into larger systems adhering to these standards.
  • Relevant Open-Source Standard: MIPI Alliance Specifications (e.g., D-PHY, CSI-2, DSI), PCI Express Base Specification.

Generated 5/19/2026, 12:50:26 PM