Obviousness

Here's an analysis of the obviousness of US patent 7989944 under 35 U.S.C. § 103, based on the prior art references cited within the patent. The analysis identifies combinations of prior art that would render the independent claims obvious and explains the motivation for a person having ordinary skill in the art (PHOSITA) to combine them.

The objective of US7989944 is to provide a method for reliably and economically embedding unpacked microcircuits into a base, combining component packaging, board manufacturing, and assembly stages. The patent emphasizes benefits such as miniaturization, improved reliability (e.g., solderless connections, lower process temperatures), the ability to create three-dimensional structures, and electromagnetic interference (EMI) protection. [cite: 7989944 Description, "Object of the invention is to create a method, by means of which unpacked microcircuits can be embedded to a base reliably but economically.", "The combination of the various process stages brings important logistic benefits and permits the manufacture of a smaller and more reliable electronic module.", "The invention also permits electromagnetic protection to be made around the component embedded in the base."]

Obviousness of Claim 1

Claim 1 describes a circuit board comprising:

1. An insulating material layer having a first side and a second side.
2. At least one first conductive pattern layer on the first side, defining a first metal plate.
3. At least one second conductive pattern layer on the second side, defining a second metal plate.
4. A component inside the insulating material layer and between the first and second metal plates, with contact areas on a first surface facing the second metal plate.
5. A hardened insulating polymer layer between the component's first surface and the second conductive pattern layer.
6. Contact openings in the hardened insulating polymer layer and conductors therein for electrical contacts between the component's contact areas and the second conductive pattern layer.

Combination of Prior Art: US6292366B1 (Intel Corporation) in combination with the general knowledge of a person having ordinary skill in the art (PHOSITA) regarding printed circuit board (PCB) design and electromagnetic interference (EMI) shielding.

Analysis:
The primary reference, US6292366B1, "Printed circuit board with embedded integrated circuit," discloses most elements of Claim 1:

• Insulating material layer: US6292366B1 teaches a substrate (10) as an insulating layer having a first and second side. [cite: 6292366B1 Fig 1]
• Conductive pattern layers: It discloses wiring (18) as a conductive pattern layer on the first side and wiring (20) as a conductive pattern layer on the second side of the substrate. [cite: 6292366B1 Fig 1]
• Component inside insulating layer: It teaches an integrated circuit (14) embedded in a cavity (12) within the substrate (10). [cite: 6292366B1 Abstract, Fig 1] The integrated circuit has leads (16) serving as contact areas on a surface, which can be oriented towards a conductive layer. [cite: 6292366B1 Fig 1]
• Hardened insulating polymer layer and contact openings/conductors: US6292366B1 describes a dielectric material (18') formed over an encapsulant (22), which covers the leads (16') of the integrated circuit. [cite: 6292366B1 Description, column 3, lines 52-53, Fig 1] Vias (20') are formed in this dielectric material (hardened insulating polymer layer) over the leads, and conductive material (24') is deposited in these vias to form electrical connections to subsequent wiring layers (part of the second conductive pattern layer). [cite: 6292366B1 Description, column 3, lines 53-58, Fig 1]

The remaining elements to explicitly address are the "first metal plate" and "second metal plate" defined by the conductive pattern layers, and the component being positioned "between" them. While US6292366B1 refers to "wiring," these are conductive layers that can be patterned to form larger conductive areas.

Motivation to Combine/Modify:
A PHOSITA, designing circuit boards for microelectronic components, would be well aware that conductive layers are routinely patterned into ground and power planes (i.e., "metal plates") in multi-layer PCB construction. This is standard practice for several known benefits:

1. Signal Integrity: Providing stable reference planes for electrical signals.
2. Power Distribution: Creating low-impedance paths for power and ground connections.
3. Electromagnetic Interference (EMI) Shielding: Enclosing sensitive components between ground planes helps mitigate electromagnetic radiation and external interference. US7989944 itself highlights EMI protection as an advantage. [cite: 7989944 Description, "The solution shown by FIG. 4D thus provides the microcircuit with excellent protection against electromagnetic interference."]
4. Thermal Management: Large copper planes can assist in dissipating heat.

Therefore, a PHOSITA seeking to improve the electrical performance, power integrity, or EMI characteristics of the embedded integrated circuit in US6292366B1 would be motivated to pattern portions of the existing conductive wiring layers into ground or power planes. Such planes would naturally enclose the embedded component, functioning as the "first" and "second metal plates" between which the component resides. This modification is a predictable result of applying known PCB design principles. Furthermore, prior art such as US6131269A, "Circuit isolation technique for RF and millimeter-wave modules," explicitly teaches the use of conductive material for electromagnetic shielding around circuit elements, providing a clear motivation for incorporating conductive structures for EMI protection. [cite: 6131269A Abstract]

Obviousness of Claim 15

Claim 15 describes a multi-layered circuit board comprising a first circuit board substructure and a second circuit board substructure on top of each other, where at least the first substructure is as defined in Claim 1.

Combination of Prior Art: US6292366B1 (Intel Corporation) (as modified for Claim 1) in combination with common knowledge in the art of multi-layer PCB fabrication and explicit teachings of stacking electronic components.

Analysis:
The foundation of Claim 15 rests on the structure defined in Claim 1, which has been argued as obvious based on US6292366B1 and PHOSITA knowledge. The additional feature is the stacking of multiple such substructures to form a multi-layered circuit board. The concept of stacking circuit boards or embedding multiple components in a three-dimensional arrangement was well-known in the prior art.

• US5227338A, "Three-dimensional memory card structure with internal direct chip attachment," describes stacking multiple circuit elements. [cite: 5227338A Abstract]
• US20010054758A1, "Three-dimensional memory stacking using anisotropic epoxy interconnections," also teaches techniques for stacking components and layers. [cite: 20010054758A1 Abstract]
• US6324067B1, "Printed wiring board and assembly of the same," describes multi-layer printed wiring boards. [cite: 6324067B1 Abstract]

Motivation to Combine:
The patent US7989944 explicitly states that "The invention can also be applied in such a way that circuit boards are assembled on top of each other, thus forming a multi-layer circuit structure, in which there are several circuit boards manufactured according to FIG. 1 set on top of each other and connected electrically to each other." [cite: 7989944 Description, "The invention can also be applied in such a way that circuit boards are assembled on top of each other, thus forming a multi-layer circuit structure, in which there are several circuit boards manufactured according to FIG. 1 set on top of each other and connected electrically to each other."] This indicates that multi-layering is a desirable outcome. A PHOSITA seeking to achieve higher component density, increased functionality, or miniaturization of electronic devices would be motivated to stack the embedded-component circuit boards (as taught by US6292366B1 and modified to include metal plates). This is a well-established design strategy in electronics. The numerous prior art references demonstrating component stacking and multi-layer PCB construction confirm that the techniques for assembling such structures were known. Therefore, combining the embedded circuit board of US6292366B1 (as modified for Claim 1) with known multi-layering techniques would be obvious.

Obviousness of Claim 32

Claim 32 defines an electronic module similar to Claim 1, but with added features:

• A hole having sidewalls defined in the insulating material layer and located between the first and second metal plates.
• A metal foil covering the sidewalls of the hole.
• A filler material in the hole between the metal foil and the microcircuit.

Combination of Prior Art: US6292366B1 (Intel Corporation) in combination with US6131269A (TRW Inc.) and general PHOSITA knowledge.

Analysis:
As established for Claim 1, US6292366B1 discloses:

• An insulating material layer with first and second conductive pattern layers (patternable into metal plates). [cite: 6292366B1 Fig 1]
• A hole (cavity 12) with sidewalls defined in the insulating material layer. [cite: 6292366B1 Fig 1]
• A microcircuit (IC 14) inside the hole, with contact areas (leads 16) on a surface. [cite: 6292366B1 Abstract, Fig 1]
• A filler material (encapsulant 22) in the hole between the microcircuit and the surrounding material. [cite: 6292366B1 Fig 1]
• A hardened insulating polymer layer and contact openings/conductors, as described for Claim 1. [cite: 6292366B1 Description, column 3, lines 52-58, Fig 1]

The distinguishing feature of Claim 32 is the "metal foil covering the sidewalls of the hole."

Motivation to Combine:
The patent US7989944 explicitly recognizes the benefit of sidewall shielding, stating that the method can be modified so that "the conductive layer 4 to be made in stage 1 C will also cover the side walls of the holes 6 made for the components" to provide EMI protection. [cite: 7989944 Description, "The invention also permits electromagnetic protection to be made around the component embedded in the base. This is because the method of FIG. 1 can be modified in such a way that the holes 6 depicted in stage 1 E can be made in connection with the making of the holes 3 carried out in stage 1 B. In that case, the conductive layer 4 to be made in stage 1 C will also cover the side walls of the holes 6 made for the components."]

The prior art reference US6131269A, "Circuit isolation technique for RF and millimeter-wave modules," directly teaches this specific feature and its motivation. It discloses forming an "isolation via wall" in a substrate around a circuit element and depositing "conductive material on the isolation via wall to form a conductive wall, which electromagnetically shields the circuit element." [cite: 6131269A Abstract]

A PHOSITA, aware of the embedded microcircuit structure of US6292366B1 (including a cavity) and also aware of the known problems of EMI and solutions like those taught in US6131269A, would be motivated to combine these teachings. The goal of improving EMI shielding for sensitive microcircuits is a known design challenge. Applying the sidewall conductive shielding technique from US6131269A to the embedded component structure of US6292366B1 would be an obvious design choice to achieve the known benefit of enhanced electromagnetic protection.