Prior art — US Patent 7969231

To identify the most relevant prior art for US patent 7969231, I will examine the patent citations listed in the Google Patents record. For each cited patent, I will provide the full citation, publication/filing date, a brief description, and discuss which claims of US7969231 it potentially anticipates under 35 U.S.C. § 102.

It's important to note that the USPTO website offers tools for patent searching, including Patent Public Search, which allows users to search databases of patents and patent application publications. The effective date of prior art for U.S. patents can be its filing date, or an earlier effective U.S. filing date under 35 U.S.C. 102(e) (pre-AIA) or 35 U.S.C. 102(a)(2) (AIA). Prior art can include patents, printed publications, public use, sales, or other public availability before the effective filing date of the claimed invention.

Disclaimer on Claims 6-8: As noted in the patent summary, a disclaimer for claims 6-8 of US7969231 was filed with an effective date of December 1, 2025, on March 24, 2026. Therefore, these claims are no longer active.

Here's an analysis of the cited prior art:

Cited Prior Art for US Patent 7969231

The following patents are cited as prior art in US7969231:

U.S. Pat. No. 5,999,475 (US5999475A)
- Full Citation: US5999475A, Mitsubishi Denki Kabushiki Kaisha, "Internal potential generation circuit that can output a plurality of potentials, suppressing increase in circuit area", published December 7, 1999.
- Publication/Filing Date: Publication Date: December 7, 1999. Filing Date: August 27, 1997.
- Brief Description: This patent describes an internal potential generation circuit with a plurality of charge pump circuits that can output multiple potentials while suppressing an increase in circuit area. It specifically mentions an internal voltage generating circuit with a first boost circuit and a second boost circuit, and a high voltage switch circuit that connects or disconnects their output nodes. The first boost circuit has a higher current supply capability and a lower boosted voltage target, while the second has a lower current supply capability and a higher boosted voltage target. During startup, the switch circuit is conductive, allowing the higher-capability first boost circuit to rapidly charge the second output node. After the first boosted voltage reaches its target, the switch becomes non-conductive, and the circuits operate independently. This is explicitly discussed in the background section of US7969231 as a conventional internal voltage generating circuit (FIG. 9-12 and accompanying description).
- Potential Anticipation (35 U.S.C. § 102): US5999475A appears to anticipate the fundamental concept of having multiple boost circuits with different characteristics and a switching mechanism to aid in faster startup of a lower current capability circuit. Specifically, it anticipates aspects related to:
  - An internal voltage generating circuit comprising a first boost circuit and a second boost circuit.
  - The relationship where the first boosted voltage is lower than the second boosted voltage, and the current supply capability of the first is larger than the second.
  - The use of a high voltage switch circuit to connect/disconnect the output nodes for faster charging.
  - The independent operation of the charge pump circuits after an initial startup phase.
This patent forms the basis of the "conventional internal voltage generating circuit 900" detailed in the background section of US7969231. Therefore, many elements of independent claims 1, 3, 6, and 7, which generally describe a first boost/charge pump circuit generating a voltage and a second boost/charge pump circuit generating a higher voltage, could be considered anticipated by US5999475A in a broad sense. However, US7969231 introduces specific improvements, such as the frequency dividing circuit and buffer circuit, to overcome limitations of this prior art. Therefore, while the core architecture is present, the specific inventive steps of US7969231 related to clock signal management would differentiate it.
U.S. Pat. No. 5,940,284 (US5940284A)
- Full Citation: US5940284A, Zilog, Inc., "Low voltage charge pump circuit", published August 17, 1999.
- Publication/Filing Date: Publication Date: August 17, 1999. Filing Date: December 18, 1997.
- Brief Description: This patent describes a low voltage charge pump circuit. The abstract mentions a charge pump circuit that generates a boosted voltage from a low supply voltage, utilizing a diode-connected transistor structure and a control circuit to regulate the output.
- Potential Anticipation (35 U.S.C. § 102): US5940284A generally addresses the construction and operation of charge pump circuits for generating boosted voltages from low supply voltages. While it covers the broad concept of a charge pump, it does not appear to disclose the specific two-stage boost circuit architecture with variable clock frequencies for startup acceleration or power efficiency as claimed in US7969231. It may anticipate the general concept of a "charge pump circuit configured to generate a voltage" as a sub-component, potentially impacting the novelty of such a broad statement in any claim (e.g., portions of Claims 1, 3, 6, 7 that refer to a "first boost circuit" or "first charge pump circuit" generating a voltage from a first voltage). However, it is unlikely to anticipate the unique combination of elements related to frequency division and clock selection for a second boost circuit.
U.S. Pat. No. 6,249,445 (US6249445B1)
- Full Citation: US6249445B1, Nec Corporation, "Booster including charge pumping circuit with its electric power consumption reduced and method of operating the same", published June 19, 2001.
- Publication/Filing Date: Publication Date: June 19, 2001. Filing Date: February 15, 1999.
- Brief Description: This patent discloses a booster circuit with a charge pumping circuit designed for reduced electric power consumption. It focuses on controlling the operation of the charge pump to minimize current drain when the output voltage reaches a desired level, often by stopping or slowing down the clock signal to the charge pump.
- Potential Anticipation (35 U.S.C. § 102): US6249445B1 anticipates methods for reducing power consumption in charge pump circuits by controlling the clock signal. This broadly relates to the concept of managing clock signals for efficiency. While US7969231 also deals with clock signal modification (frequency division), its primary inventive step lies in reducing startup time and then operating the second charge pump at a reduced frequency for stable supply and improved efficiency of the first boost circuit, rather than simply stopping the clock once a target voltage is reached. It might anticipate the idea of changing the "frequency of a clock signal to be supplied to the second charge pump circuit" (Claim 6, which is disclaimed) or changing the "length of a period in which a clock signal...is in a high state" (Claim 7, which is disclaimed), if those changes are for power reduction. However, the specific combination with the two-stage boost architecture and the initial high-frequency operation for fast startup, followed by a reduced frequency, is not clearly anticipated.
U.S. Pat. No. 6,278,317 (US6278317B1)
- Full Citation: US6278317B1, International Business Machines Corporation, "Charge pump system having multiple charging rates and corresponding method", published August 21, 2001.
- Publication/Filing Date: Publication Date: August 21, 2001. Filing Date: October 29, 1999.
- Brief Description: This patent describes a charge pump system with multiple charging rates. The system adjusts its charging rate, for instance, by changing the frequency of the clock signal, to optimize power consumption or startup time. It may use a higher frequency for faster charging and then a lower frequency for maintenance.
- Potential Anticipation (35 U.S.C. § 102): US6278317B1's disclosure of a charge pump system having multiple charging rates and methods for achieving this (e.g., by adjusting clock frequency) directly bears on the inventive features of US7969231. Specifically, the idea of changing the frequency of a clock signal supplied to a charge pump circuit in accordance with a control signal (Claim 6, disclaimed) or changing the length of a period in which a clock signal is in a high state (Claim 7, disclaimed) to achieve different charging rates for startup and stable operation is a core concept. This patent could potentially anticipate the broad concept of adapting the clock frequency to the second boost circuit as described in claims 6 and 7. However, US7969231's claims specify a two-stage boost architecture where the first boost circuit's output feeds the second, and the frequency division is applied to the second boost circuit's clock to manage startup and then allow the first circuit to concentrate current supply to its own load, which may represent a more specific combination not fully disclosed in US6278317B1.
U.S. Patent Application Publication No. 2004/0095806 (US20040095806A1)
- Full Citation: US20040095806A1, Matsushita Electric Industrial Co., Ltd., "Boosting circuit and non-volatile semiconductor storage device containing the same", published May 20, 2004.
- Publication/Filing Date: Publication Date: May 20, 2004. Filing Date: November 19, 2002.
- Brief Description: This application describes a boosting circuit and a non-volatile semiconductor storage device containing it. It may address improvements in power supply for memory devices, including aspects of charge pump operation or efficiency.
- Potential Anticipation (35 U.S.C. § 102): Without a more detailed description of US20040095806A1's content, it's difficult to pinpoint specific anticipations. Given its general title, it likely covers boosting circuits for non-volatile memory, which is a common application for US7969231. If it discloses a multi-stage boost architecture or clock control for charge pumps, it could potentially anticipate broad aspects of the claims. However, based solely on the title, it's unlikely to anticipate the specific combination of a frequency dividing circuit and buffer circuit controlling the clock signal to a second boost circuit that takes its input from a first boost circuit, as detailed in independent claims 1 and 3 of US7969231.
U.S. Pat. No. 6,980,045 (US6980045B1)
- Full Citation: US6980045B1, Xilinx, Inc., "Merged charge pump", published December 27, 2005.
- Publication/Filing Date: Publication Date: December 27, 2005. Filing Date: December 5, 2003.
- Brief Description: This patent describes a "merged charge pump" which likely refers to a charge pump design that integrates multiple functions or stages to achieve a desired output voltage or current, possibly with area or efficiency benefits.
- Potential Anticipation (35 U.S.C. § 102): The term "merged charge pump" suggests an integration or combination of charge pump elements. This could potentially relate to the concept of multiple charge pump circuits working in conjunction, but the details of such a merger and its control mechanisms would be critical. It is not immediately apparent from the title or brief description that it would anticipate the specific frequency division and clock selection mechanism for a second boost circuit receiving input from a first boost circuit as claimed in US7969231.
U.S. Patent Application Publication No. 2007/0222498 (US20070222498A1)
- Full Citation: US20070222498A1, Freescale Semiconductor Inc., "Slew rate control of a charge pump", published September 27, 2007.
- Publication/Filing Date: Publication Date: September 27, 2007. Filing Date: March 24, 2006.
- Brief Description: This application focuses on slew rate control of a charge pump. Slew rate refers to the rate of change of voltage, and controlling it in a charge pump can impact its startup time, stability, and power consumption. This often involves dynamic adjustment of internal parameters, including clock frequency or drive strength.
- Potential Anticipation (35 U.S.C. § 102): Slew rate control of a charge pump, particularly during startup, directly relates to the problem US7969231 aims to solve (reducing setup time). If US20070222498A1 discloses controlling the slew rate by dynamically changing the clock frequency to a charge pump, it could be highly relevant to claims 6 and 7 (both disclaimed) concerning changing the frequency or high-state period of the clock signal. Depending on the specifics, it might also anticipate aspects of claims 1 and 3 regarding dynamically adjusting clock signals to a boost circuit for performance optimization, especially during startup.
U.S. Pat. No. 7,579,902 (US7579902B2)
- Full Citation: US7579902B2, Atmel Corporation, "Charge pump for generation of multiple output-voltage levels", published August 25, 2009.
- Publication/Filing Date: Publication Date: August 25, 2009. Filing Date: December 11, 2006.
- Brief Description: This patent describes a charge pump capable of generating multiple output-voltage levels. This implies the ability to provide different boosted voltages, possibly for different applications within a device.
- Potential Anticipation (35 U.S.C. § 102): The ability to generate multiple output-voltage levels is a characteristic shared with US7969231, which produces a first boosted voltage (VPUMP1) and a second, higher boosted voltage (VPUMP2). However, merely generating multiple voltages does not necessarily anticipate the specific architecture and control mechanisms of US7969231, particularly the cascaded boost circuits with frequency division for the second stage. It might anticipate the general concept of an internal voltage generating circuit outputting multiple boosted voltages, which is a broad aspect underlying the invention.
U.S. Pat. No. 7,592,856 (US7592856B2)
- Full Citation: US7592856B2, Rohm Co., Ltd., "Charge pump circuit driver circuit having a plurality of oscillators", published September 22, 2009.
- Publication/Filing Date: Publication Date: September 22, 2009. Filing Date: December 3, 2004.
- Brief Description: This patent describes a charge pump circuit driver circuit that utilizes a plurality of oscillators. Having multiple oscillators could allow for different clock frequencies or phases to be generated and applied to the charge pump, potentially for efficiency or performance reasons.
- Potential Anticipation (35 U.S.C. § 102): The use of a "plurality of oscillators" to drive a charge pump circuit is highly relevant to US7969231's frequency dividing circuit and buffer circuit, which effectively provide a choice between a high-frequency clock signal (CLK) and a lower-frequency clock signal (FCK) to the second boost circuit. This patent could potentially anticipate the concept of generating and selecting different clock signals for a charge pump. Specifically, it could be argued to anticipate parts of claims 1 and 3 that involve a frequency dividing circuit generating a second clock signal from a first and a buffer circuit selecting between them. The key distinction for US7969231 would lie in the specific application of this variable clocking within the cascaded boost circuit context to achieve the stated benefits of reduced startup time and improved efficiency for the first boost circuit.
U.S. Pat. No. 7,605,639 (US7605639B2)
- Full Citation: US7605639B2, Hynix Semiconductor, Inc., "Internal voltage generator of semiconductor memory device", published October 20, 2009.
- Publication/Filing Date: Publication Date: October 20, 2009. Filing Date: April 18, 2007.
- Brief Description: This patent describes an internal voltage generator for a semiconductor memory device. Such generators typically include charge pump circuits and associated control logic to provide various internal operating voltages required by the memory.
- Potential Anticipation (35 U.S.C. § 102): Similar to US20040095806A1, this patent generally describes an internal voltage generator for memory devices. Without more specific details of its internal architecture and control mechanisms, it's difficult to identify precise anticipatory elements. It likely anticipates the broad context of the invention (voltage generation in semiconductor memory). However, it's unlikely to anticipate the specific combination of cascaded boost circuits with frequency division and selection for the second stage's clock signal as claimed in US7969231.
U.S. Pat. No. 7,782,120 (US7782120B2)
- Full Citation: US7782120B2, Hynix Semiconductor Inc., "Internal voltage generating circuit", published August 24, 2010.
- Publication/Filing Date: Publication Date: August 24, 2010. Filing Date: October 4, 2007.
- Brief Description: This patent describes an internal voltage generating circuit. It would likely detail a power supply circuit for an integrated circuit, possibly including charge pump mechanisms.
- Potential Anticipation (35 U.S.C. § 102): Like the previous entry, this patent has a very general title. It broadly covers internal voltage generating circuits, which is the field of US7969231. Specific details of its internal workings would be needed to assess potential anticipation. It might anticipate general aspects of internal voltage generation, but not necessarily the specific combination of a cascaded boost circuit with adaptive clock frequency control for the second stage.

Summary of Most Relevant Prior Art:

Based on the descriptions, US5999475A is highly relevant as it describes a conventional internal voltage generating circuit that serves as the starting point for US7969231, particularly regarding the two-stage boost circuit and the initial connection via a high voltage switch for faster charging. US6278317B1 and US7592856B2 are also very relevant as they disclose charge pump systems with multiple charging rates or multiple oscillators for driving charge pumps, which directly relates to the frequency control aspects of US7969231. These patents could potentially anticipate the general idea of varying the clock frequency of a charge pump.

The specific inventive contribution of US7969231 appears to be the novel combination of a cascaded boost architecture (where the first boost circuit's output is the input for the second boost circuit) with the dynamic clock frequency selection and division for the second boost circuit, controlled to optimize both startup time and subsequent operational efficiency of the overall system. The disclaimer of claims 6-8 further emphasizes that the invention's novelty is not merely in changing frequency but in how it's integrated into the two-stage architecture for specific performance benefits.