Obviousness

Obviousness Analysis of US Patent 7969231 under 35 U.S.C. § 103

This analysis addresses the obviousness of US patent 7969231, focusing on independent claims 1 and 3, as claims 6-8 have been disclaimed. The analysis considers the prior art cited within US7969231 and other references provided.

1. Claims to be Analyzed:

• Claim 1 (Independent): An internal voltage generating circuit comprising:

  • a first boost circuit provided between a first voltage and a first terminal;
  • a second boost circuit provided between the first terminal and a second terminal;
  • a frequency dividing circuit configured to divide a first clock signal to be supplied to the first boost circuit to generate a second clock signal; and
  • a buffer circuit configured to select and supply the first clock signal or the second clock signal to the second boost circuit.

• Claim 3 (Independent): An internal voltage generating circuit comprising:

  • a first charge pump circuit configured to generate a second voltage from a first voltage;
  • a second charge pump circuit configured to generate a third voltage from the second voltage;
  • a frequency dividing circuit configured to divide a first clock signal to generate a second clock signal; and
  • a buffer circuit configured to select the first clock signal or the second clock signal and generate a third clock signal,
  • wherein the third clock signal is supplied to the second charge pump circuit.

2. Primary Prior Art Reference:

The patent US7969231 itself details a conventional internal voltage generating circuit 900, disclosed in U.S. Pat. No. 5,999,475 (Mitsubishi Denki Kabushiki Kaisha), in its background section (FIG. 9 and associated description). This serves as a strong primary reference for an obviousness argument.

• Disclosure of US5999475: US5999475 describes an internal voltage generating circuit 900 including a first boost circuit 901 and a second boost circuit 902. Both boost circuits perform operation in synchronization with a clock signal CLK and a complementary clock signal XCLK. The first boost circuit 901 outputs a first boosted voltage VPUMP1 through a first output node N1, and the second boost circuit 902 outputs a second boosted voltage VPUMP2 through a second output node N2. A high voltage switch circuit 903 connects or disconnects a path between the first output node N1 and the second output node N2.
  • Crucially, in the conventional circuit, both the first charge pump circuit 906 (part of 901) and the second charge pump circuit 909 (part of 902) receive a power source voltage VDD as their input.
  • The conventional circuit operates in two phases: During "Phase 1," the switch 903 is conductive, allowing the first charge pump 906 (with high current supply capability) to rapidly charge both N1 and N2 to VPUMP1. During "Phase 2," the switch 903 becomes non-conductive, and the second charge pump 909 (with low current supply capability) independently charges N2 to VPUMP2.
• Problem Addressed by US7969231 in relation to US5999475: The conventional circuit faces a trade-off where reducing the setup time of the second charge pump during Phase 2 by increasing its boost capacitances (Cb1-Cb6) leads to increased circuit area and potentially requires additional smoothing capacitance to prevent ripple, further increasing area.

3. Missing Elements in US5999475 for Claims 1 and 3 of US7969231:

Based on the description of US5999475 within US7969231, the following key elements of Claims 1 and 3 are not directly present:

• Hierarchical Boosting Input: The "second boost circuit provided between the first terminal and a second terminal" (Claim 1) or "second charge pump circuit configured to generate a third voltage from the second voltage" (Claim 3). In US5999475, both charge pumps receive VDD, not the output of the first boost circuit.
• Frequency Dividing Circuit: A circuit configured to divide a clock signal.
• Buffer Circuit for Clock Selection: A circuit configured to select and supply either the original or frequency-divided clock signal to the second boost circuit.

4. Secondary Prior Art References and Motivation to Combine:

A person having ordinary skill in the art (PHOSITA) would be motivated to combine US5999475 with other known techniques to address the limitations identified in the conventional art.

Combination 1: US5999475 + General Knowledge of Multi-Stage Boosting + US6278317B1 / US7592856B2

• Motivation for Hierarchical Boosting (Connecting First Terminal to Second Boost Circuit Input):

  • Facing the problem in US5999475 of the second charge pump's slow setup time during Phase 2 or the undesirable increase in circuit area required to speed it up, a PHOSITA would recognize that supplying the second charge pump with an already boosted voltage (VPUMP1 from the first stage) instead of the lower VDD would inherently reduce the voltage difference the second stage needs to generate. This is a common and obvious design principle in multi-stage voltage generation to achieve higher voltages or faster boosting with fewer stages or smaller capacitors. By providing a pre-boosted input from the high current capability first charge pump, the second charge pump's setup time would be naturally reduced.

• Motivation for Frequency Dividing Circuit and Buffer Circuit (Dynamic Clock Frequency Reduction):

  • Even with the hierarchical input, the second charge pump still draws current from the first. US7969231 notes that after the initial setup, a high operating frequency for the second charge pump could still impact the stability of the first charge pump's output (VPUMP1).
  • US6278317B1 (International Business Machines Corporation) - "Charge pump system having multiple charging rates and corresponding method". This patent discloses a "frequency regulated charge pump" where "the frequency fclk is determined by a controller circuit that measures the difference between the target VOUT voltage and the real VOUT". This directly teaches dynamically varying the clock frequency of a charge pump.
  • US7592856B2 (Rohm Co., Ltd.) - "Charge pump circuit driver circuit having a plurality of oscillators". This reference implies the capability to generate or select from different clock frequencies.
  • A PHOSITA, seeking to further optimize the system of US5999475 (as modified with hierarchical input) to ensure stability of VPUMP1 after VPUMP2 has reached its target voltage, would be motivated to reduce the current drawn by the second charge pump from the first. Reducing the clock frequency of a charge pump is a well-known method to reduce its current consumption and ripple. Therefore, it would be obvious to incorporate a mechanism, like a frequency dividing circuit and a buffer for selecting between an original fast clock (for rapid initial setup) and a divided, slower clock (for maintenance), to supply the second charge pump. This allows current supply to be concentrated into the output load of the first charge pump, suppressing output voltage fluctuation, as explicitly stated as a benefit in US7969231. The frequency dividing circuit and buffer circuit are standard components for implementing such a clock selection scheme.

5. Conclusion on Obviousness:

Claims 1 and 3 of US7969231 would have been obvious to a person having ordinary skill in the art at the time of the invention. The combination of the conventional internal voltage generating circuit of US5999475 with:

1. The well-known engineering principle of hierarchical voltage boosting (using the output of a first boost stage as the input for a subsequent boost stage) to reduce setup time for the second stage.
2. The teachings of US6278317B1 regarding frequency-regulated charge pumps or US7592856B2 regarding multiple oscillators for charge pump clocking, for the purpose of dynamically adjusting the clock frequency of the second boost circuit.

The motivation for this combination arises from directly addressing the identified shortcomings of the conventional art in US5999475, namely the desire to reduce the setup time for the second boosted voltage (VPUMP2) without increasing circuit area, and to improve the stability and efficiency of the first boosted voltage (VPUMP1) once the second stage is active. The frequency dividing circuit and buffer circuit are standard components that a PHOSITA would readily employ to achieve the desired clock signal modification.