Prior art

I have analyzed US patent 7836381 and identified its prior art references from the "Citations" section of the provided patent text. The priority date for US7836381 is October 12, 2004. Any prior art with a priority date before this date is generally relevant for anticipation under 35 U.S.C. § 102.

Here is an analysis of the most relevant prior art cited by US7836381:

Prior Art for US7836381

1. US6337877B1

• Full Citation: US6337877B1: "Method and apparatus for scaling modem transfer capacity in a multi-channel communications system."
• Publication Date: 2002-01-08
• Priority Date: 1998-08-27
• Assignee: Legerity, Inc.
• Brief Description: This patent describes a method and apparatus for scaling modem transfer capacity in a multi-channel communication system, suggesting an awareness of multi-channel communication needs and potentially resource management in such systems.
• Potential Anticipation (35 U.S.C. § 102): This patent's focus on scaling modem transfer capacity in multi-channel systems could potentially anticipate the general concept of managing resources across different communication paths. While it doesn't explicitly mention shared memory for interleavers/deinterleavers, it lays groundwork for multi-channel modem operation which is a prerequisite for US7836381's latency paths. It might generally anticipate the context of allocating resources based on communication needs, which underlies claims 1 and 5 of US7836381.

2. EP1225735A1

• Full Citation: EP1225735A1: "Data communication system."
• Publication Date: 2002-07-24
• Priority Date: 2000-07-07
• Assignee: Matsushita Electric Industrial Co., Ltd.
• Brief Description: This European patent describes a data communication system. Without further detail, its relevance to specific sharing mechanisms for interleavers and deinterleavers is less clear from the title alone.
• Potential Anticipation (35 U.S.C. § 102): The broad title "Data communication system" makes it difficult to pinpoint specific anticipation without reviewing its content. However, depending on its disclosed methods for data handling or resource management in a communication system, it could broadly relate to the environment in which US7836381 operates.

3. EP1246409A1

• Full Citation: EP1246409A1: "Packet retransmission system, packet transmission device, packet reception device, packet retransmission method, packet transmission method and packet reception method."
• Publication Date: 2002-10-02
• Priority Date: 2000-10-05
• Assignee: Mitsubishi Denki Kabushiki Kaisha
• Brief Description: This patent details a packet retransmission system and related devices and methods. Retransmission mechanisms often involve buffering and memory management for packets.
• Potential Anticipation (35 U.S.C. § 102): The focus on packet retransmission implies buffer management and memory usage in transceivers. This could potentially anticipate aspects of shared memory allocation in a general sense, particularly for buffering data that might be subject to interleaving/deinterleaving, which forms a part of US7836381's claims 1 and 5.

4. US20030067877A1

• Full Citation: US20030067877A1: "Communication system and techniques for transmission from source to destination."
• Publication Date: 2003-04-10
• Priority Date: 2001-09-27
• Assignee: Raghupathy Sivakumar
• Brief Description: This publication relates to communication systems and techniques for data transmission.
• Potential Anticipation (35 U.S.C. § 102): Similar to EP1225735A1, the broad title offers limited specific insight into anticipation. However, if it discusses optimization of transmission paths or resource handling, it could touch upon the general problem addressed by US7836381.

5. WO2003063060A2

• Full Citation: WO2003063060A2: "Asymmetric digital subscriber line modem apparatus and methods therefor."
• Publication Date: 2003-07-31
• Priority Date: 2002-01-24
• Assignee: Broadcom Corporation
• Brief Description: This international publication describes ADSL modem apparatus and methods. ADSL systems inherently deal with varying data rates and latency requirements, similar to the context of US7836381.
• Potential Anticipation (35 U.S.C. § 102): Given that US7836381 specifically discusses DSL systems (ADSL, VDSL), this reference on ADSL modems is highly relevant. It could potentially anticipate the use of multiple latency paths, or the need to manage resources for different application requirements (e.g., data rate, latency, BER), as described in claims 1-4 and 5-8, within a DSL context.

6. US6707822B1

• Full Citation: US6707822B1: "Multi-session asymmetric digital subscriber line buffering and scheduling apparatus and method."
• Publication Date: 2004-03-16
• Priority Date: 2000-01-07
• Assignee: Agere Systems Inc.
• Brief Description: This patent directly addresses buffering and scheduling in multi-session ADSL, which is highly relevant to memory management and handling different data streams with varying requirements.
• Potential Anticipation (35 U.S.C. § 102): This patent appears highly relevant as it explicitly discusses "buffering and scheduling" in ADSL. This could directly anticipate the shared memory concept (claims 1 and 5), the allocation based on data rates (claims 1 and 5), and the ability to handle multiple "latency paths" for different applications, even if it doesn't specifically mention "interleaver/deinterleaver memory." The concepts of managing resources for multiple sessions and diverse requirements are central to US7836381.

7. US20040114536A1

• Full Citation: US20040114536A1: "Method for communicating information on fast and slow paths."
• Publication Date: 2004-06-17
• Priority Date: 2002-10-16
• Assignee: O'rourke Aidan
• Brief Description: This publication describes methods for communicating information using "fast and slow paths," which directly relates to the concept of latency paths and different application requirements.
• Potential Anticipation (35 U.S.C. § 102): This reference is very pertinent due to its explicit mention of "fast and slow paths," which directly correlates with the "latency paths" concept of US7836381 used for applications with different latency requirements (e.g., voice vs. video). This could anticipate the fundamental idea of managing multiple paths with different delay characteristics, which is a key driver for shared resource allocation in claims 1-4 and 5-8.

8. US6775320B1

• Full Citation: US6775320B1: "Method and a multi-carrier transceiver supporting dynamic switching between active application sets."
• Publication Date: 2004-08-10
• Priority Date: 1999-03-12
• Assignee: Aware, Inc.
• Brief Description: This patent, from the same original assignee (Aware Inc.) as US7836381, specifically describes multi-carrier transceivers supporting dynamic switching between application sets, and is explicitly mentioned in the background of US7836381 as describing DSL systems supporting multiple applications and FCI blocks (latency paths).
• Potential Anticipation (35 U.S.C. § 102): This is a highly relevant prior art, explicitly cited in the background of US7836381 for describing "DSL systems supporting multiple applications and multiple framer/coder/interleaver FCI blocks (an FCI block is also referred to as a latency path)." It directly anticipates the concept of multiple latency paths, and the need to manage different application requirements, forming the foundation for US7836381's resource sharing. It would likely anticipate the broad setup for allocating resources to multiple latency paths as recited in the preambles of claims 1 and 5, and the general idea of supporting applications with varying data rate, latency, and BER requirements (claims 2-4, 6-8).

9. US6778589B1

• Full Citation: US6778589B1: "Symbol synchronous device and frequency hopping receiver."
• Publication Date: 2004-08-17
• Priority Date: 1998-10-09
• Assignee: Futaba Denshi Kogyo Kabushiki Kaisha
• Brief Description: This patent describes a symbol synchronous device and frequency hopping receiver. It is also explicitly mentioned in the background of US7836381 alongside US6775320B1 as describing DSL systems supporting multiple applications and FCI blocks.
• Potential Anticipation (35 U.S.C. § 102): Similar to US6775320B1, this patent is explicitly cited in the background of US7836381 for describing DSL systems with multiple FCI blocks/latency paths. It therefore broadly anticipates the communication system environment and the existence of multiple latency paths for different applications, as alluded to in the context of claims 1 and 5.

10. US20050180323A1

• Full Citation: US20050180323A1: "System for transmitting high quality speech signals on a voice over Internet protocol network."
• Publication Date: 2005-08-18
• Priority Date: 2004-02-12
• Assignee: Beightol Dean D.
• Brief Description: This publication focuses on transmitting high-quality speech signals over VoIP, implying specific requirements for latency and quality that would necessitate particular resource handling.
• Potential Anticipation (35 U.S.C. § 102): While its publication date is after US7836381's priority date (2004-10-12), its priority date (2004-02-12) is before US7836381's priority date, making it prior art. The specific focus on voice transmission over IP, and ensuring high quality, means it likely addresses latency and error rate requirements, which are factors for allocation in US7836381's claims 2-4 and 6-8. If it discusses memory or processing resource management to meet these QoS (Quality of Service) parameters for voice, it could be highly anticipatory.

11. US20060088054A1

• Full Citation: US20060088054A1: "Resource sharing in a telecommunications environment."
• Publication Date: 2006-04-27
• Priority Date: 2004-10-12
• Assignee: Aware, Inc.
• Brief Description: This is an earlier publication of an application from the same assignee, Aware, Inc., and shares the same priority date as US7836381. It likely describes very similar or identical subject matter regarding resource sharing.
• Potential Anticipation (35 U.S.C. § 102): This is a family member (an earlier publication of a related application) with the same priority date as US7836381. Therefore, it is generally considered part of the same inventive entity and would not typically anticipate under §102 against itself. However, it represents closely related work by the same inventors/assignee. It provides strong evidence of what was known and invented by Aware, Inc. around the priority date, encompassing the core concepts of sharing memory and processing resources, particularly for interleavers/deinterleavers, as claimed in US7836381.

12. US20090300450A1

• Full Citation: US20090300450A1: "Packet retransmission and memory sharing."
• Publication Date: 2009-12-03
• Priority Date: 2006-04-12
• Assignee: Aware, Inc.
• Brief Description: This patent publication from the same assignee focuses on packet retransmission and memory sharing.
• Potential Anticipation (35 U.S.C. § 102): Its priority date (2006-04-12) is after US7836381's priority date (2004-10-12). Therefore, it does not anticipate US7836381 under 35 U.S.C. § 102. It would likely be considered a later development or improvement by the same assignee.

Most Relevant Prior Art Summary:
The most directly relevant prior art appear to be:

• US6775320B1 and US6778589B1: Explicitly mentioned in the background of US7836381 for describing DSL systems with multiple latency paths/FCI blocks, providing the foundational context for the invention.
• US6707822B1: Directly addresses "buffering and scheduling" in multi-session ADSL, which strongly relates to shared memory and allocation based on differing requirements.
• US20040114536A1: Explicitly discusses "fast and slow paths," directly correlating to US7836381's latency paths.
• WO2003063060A2: Addresses ADSL modems, providing the specific communication environment for US7836381.
• US20050180323A1: With a priority date earlier than US7836381, this reference focuses on QoS for voice over IP, which would necessitate management of latency and error rates through resource allocation, thus potentially anticipating the parameter-based allocation in claims 2-4 and 6-8.

These references collectively establish the state of the art concerning multi-path communication, buffering, scheduling, and different QoS requirements within DSL and similar environments prior to US7836381's priority date.