Obviousness

Under 35 U.S.C. § 103, a patent claim is considered obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). The analysis involves identifying a motivation to combine prior art references to arrive at the claimed invention with a reasonable expectation of success.

US Patent 7836381 focuses on sharing memory and processing power among multiple transmitter and/or receiver latency paths in a telecommunications transceiver, particularly in DSL systems. The patent explicitly identifies the challenge it addresses: "a latency path is a complicated digital circuit that requires a large amount of memory and processing power. An interleaver within a latency path can consume a large amount of memory... Likewise, the coding block... consumes a large amount of processing power. In general, as the number of latency paths increase, the memory and processing power requirements for a communication system become larger."

The patent references U.S. Pat. Nos. 6,775,320 and 6,778,589 as background, stating that they "describe DSL systems supporting multiple applications and multiple framer/coder/interleaver FCI blocks (an FCI block is also referred to as a latency path)." These prior art patents teach a system where different applications (e.g., video, voice, internet access) with varying requirements (data rate, latency, bit error rate (BER)) are supported by dedicated latency paths, each typically having its own framer, coder, and interleaver/deinterleaver.

A PHOSITA in the field of telecommunications and computer architecture, at the time of the invention, would have been motivated to combine the teachings of these prior art references with the general knowledge of resource optimization techniques to arrive at the claimed invention.

Combination of Prior Art: U.S. Pat. No. 6,775,320 (or U.S. Pat. No. 6,778,589) and General Knowledge of Resource Sharing in Computing and Telecommunication Systems

Primary Reference: U.S. Pat. No. 6,775,320 (or U.S. Pat. No. 6,778,589)
These patents disclose DSL systems designed to support multiple applications, each requiring different quality-of-service (QoS) parameters such as data rate, latency, and BER. To accommodate these diverse needs, the systems employ multiple dedicated latency paths, with each path including its own framer, coder, and interleaver. This architecture inherently leads to increased memory and processing power demands as more latency paths are added.

Supplemental Prior Art/General Knowledge of a PHOSITA:
A PHOSITA would be well-versed in the principles of resource sharing and dynamic allocation in various computing and communication systems. It is a well-known technique to optimize the use of finite resources, such as memory and processing units, by allowing multiple modules to share a common pool, especially when individual modules do not require their peak resource capacity simultaneously. This reduces overall hardware costs, power consumption, and system complexity. The concept of interleaved memory, for instance, is known in computing to improve throughput by distributing memory access across multiple banks. Furthermore, routine communication between connected transceivers regarding their capabilities and resource availability during initialization or operation (SHOWTIME) is a standard practice in establishing and maintaining efficient communication links.

Motivation to Combine:
The problem explicitly highlighted by US7836381, stemming from the architecture described in U.S. Pat. No. 6,775,320, is the escalating memory and processing requirements due to the dedicated nature of each latency path's interleaver and coder. A PHOSITA, aiming to address this known problem, would be motivated to apply the well-understood principles of resource sharing to reduce the redundant allocation of memory and processing power. This motivation aligns with the "known-techniques" rationale, where a known technique (resource sharing) is applied to improve a device (multi-latency path DSL transceiver) in a predictable way (reduced resource consumption, increased efficiency).

Obviousness Analysis of Independent Claims 1 and 5:

Both independent claims (Claim 1 focusing on interleaver-first allocation, Claim 5 on deinterleaver-first allocation) describe a computer-readable medium with instructions for a method of allocating shared memory in a transceiver. The core elements are:

1. Transmitting/receiving a message during initialization specifying maximum memory: In a DSL system with shared resources, it would be an obvious engineering decision for communicating transceivers to exchange information about their memory capabilities (e.g., maximum shared memory available for interleavers/deinterleavers). This information is crucial for negotiating and configuring compatible system parameters during initialization or SHOWTIME.
2. Determining memory required by interleaver/deinterleaver for Reed-Solomon (RS) coded data: The memory requirements for interleavers/deinterleavers are directly related to parameters like interleaver depth and codeword size, which are fundamental to error correction (e.g., for RS codes). Determining these requirements is inherent to the design and operation of any interleaver/deinterleaver, whether dedicated or shared.
3. Allocating a first number of bytes of shared memory to an interleaver/deinterleaver (not exceeding maximum): Given the motivation to share resources, allocating a portion of a common memory pool to an interleaver or deinterleaver is a direct application of dynamic resource allocation techniques. The constraint that the allocation does not exceed a specified maximum is a standard practice in resource management.
4. Allocating a second number of bytes of shared memory to a deinterleaver/interleaver: This element further exemplifies the shared memory concept, where different functional units (transmitter-side interleaver and receiver-side deinterleaver, or multiple interleavers/deinterleavers) draw from the same memory pool.
5. Simultaneous interleaving/deinterleaving using allocated shared memory: In a full-duplex transceiver, transmit (interleaving) and receive (deinterleaving) operations occur concurrently. If a shared memory is allocated for both, their simultaneous use of their respective portions is a natural consequence of the transceiver's operation.
6. Determining allocation based on communication parameters (impulse noise protection, latency, BER) (Claims 2-4, 6-8): U.S. Pat. No. 6,775,320 already establishes that different applications have different QoS requirements (latency, BER, data rate). Since interleaver memory directly impacts these parameters (e.g., larger interleaver depth improves burst error correction but increases latency), it would be an obvious design choice for a PHOSITA to base the allocation of shared memory on these known application-specific requirements.

Conclusion:
The combination of the multi-latency path architecture described in U.S. Pat. No. 6,775,320 (or U.S. Pat. No. 6,778,589) with the pervasive general knowledge of resource sharing, dynamic allocation, and communication negotiation in computing and telecommunication systems would render the claims of US7836381 obvious to a PHOSITA. The motivation to combine these elements stems from the recognized problem of inefficient resource utilization in dedicated multi-path systems, leading to a predictable solution of implementing shared, dynamically allocated resources with appropriate inter-transceiver communication for configuration.