Prior art

The USPTO database confirms the existence of US patent 7685393, titled "Synchronous memory read data capture," with a publication date of March 23, 2010.

The provided full patent text for US7685393 explicitly identifies one prior art patent: U.S. Pat. No. 6,889,336.

Due to the nature of the search tool, direct access to the full text, abstract, or detailed claims of US Patent 6,889,336 from the search snippets was not possible. Therefore, a comprehensive analysis of its content for potential anticipation of claims in US7685393 under 35 U.S.C. § 102 cannot be performed with high confidence and direct grounding in the search results at this time.

However, based on the information available within the text of US7685393, the following details for U.S. Pat. No. 6,889,336 are provided:

Prior Art Reference: US 6,889,336 B2

• Full Citation: U.S. Pat. No. 6,889,336, granted to A. M. Schoenfeld et al., titled (as inferred from the context of US7685393) "Method and apparatus for enabling a data strobe in a memory controller" or a similar title relating to DDR SDRAM and bidirectional data strobes.
• Publication Date: May 3, 2005.
• Filing Date: The filing date was not directly obtainable from the search results, but it would precede the publication date of May 3, 2005.
• Brief Description (as referenced by US7685393): US 6,889,336 discloses "An application of a bidirectional data strobe signal to DDR SDRAM." It describes the use of a bidirectional data strobe signal for DDR SDRAM memory systems.
• Potential Anticipation under 35 U.S.C. § 102: Without direct access to the claims and full description of US 6,889,336 from current search results, a definitive determination of which specific claims of US7685393 it potentially anticipates cannot be made. However, given that US7685393 itself cites this patent in its background for disclosing the "application of a bidirectional data strobe signal to DDR SDRAM," it likely anticipates fundamental aspects related to the concept of using bidirectional data strobes in DDR SDRAM.
  • For example, claims in US7685393 that broadly relate to "a method for controlling a synchronous memory comprising... receiving a data strobe signal synchronously with the data signal" (Claim 2, last part) or "a memory that has a bidirectional read/write bus with source synchronous clocking and a bidirectional data strobe" (Claim 18, preamble) could potentially be generally related to the subject matter of US 6,889,336. However, the inventive steps of US7685393 primarily revolve around measuring a read delay using a single initialization sample derived from a Gray code sequence and dynamically adjusting DQS enable timing, which are specific methods and circuits that would need to be compared directly against the claims of US 6,889,336 for a precise anticipation analysis.