Obviousness

Obviousness Analysis of US Patent 7,685,393 under 35 U.S.C. § 103

This analysis identifies combinations of prior art references that would render the claims of US patent 7,685,393 obvious to a person having ordinary skill in the art (PHOSITA), along with the motivation for such combinations. The analysis relies on the prior art explicitly described within the '393 patent itself, particularly U.S. Pat. No. 6,889,336 to Schoenfeld et al. and the LSI Logic 0.11 µm DDR2 PHY document cw000733—1—0 dated February 2005.

The '393 patent addresses several challenges in synchronous memory read data capture, specifically for Double Data Rate (DDR) Synchronous DRAM (SDRAM) systems using bidirectional data strobes (DQS). These challenges include determining the optimal timing for the DQS enable signal during system initialization, adjusting for timing drift during operation, and transferring data from the DQS clock domain to the system clock domain.

Core Problem Addressed by the Patent

The '393 patent highlights that for DDR400 and higher data rates, the read data timing can vary significantly, exceeding the DQS preamble interval, thus rendering fixed timing solutions for DQS enablement unreliable. It notes that existing DQS gating approaches, such as those described in the LSI Logic DDR2 PHY document, have limitations:

• "Programmable GATEON": Requires iterative read data training, significant initialization time, higher-level controller intelligence, and cannot accommodate timing drift.
• "Feedback GATEON": Requires additional pins, PCB traces, and consumes power, while not perfectly matching the actual command-to-read data loop-around delay.
• "External GATEON": Also requires additional pins and interconnects.

The invention proposes a "snap-shot data training" method using a Gray code initialization sequence and a lookup table for efficient initial DQS enable timing determination, a drift detection mechanism, and a clock domain crossing circuit.

Obviousness Arguments Based on Prior Art Combinations

1. Snap-Shot Read Delay Determination (Claims 1, 3-9, 17, 18, 20)

Claim 1 describes a method for establishing a read data path delay by writing an initialization sequence, sending a read command, sampling the returned data signals at a predetermined time to produce a single initialization sample, and using this sample to determine the read data path delay. Claims 3-8 specify the use of a Gray code sequence and sampling its bits with four clock phases. Claim 9 adds storing expected initialization samples for lookup.

• Prior Art Teachings:

  • Schoenfeld '336 (and general DDR SDRAM knowledge): Discloses the context of DDR SDRAM with bidirectional data strobe signals. A PHOSITA would be familiar with the architecture and operation of such memory systems.
  • LSI Logic "Programmable GATEON": Explicitly teaches the necessity of "read data training" to determine the optimal DQS enable timing. This involves performing read operations and analyzing the received data to set a programmable delay register. This method implicitly requires writing a known initialization sequence and reading it back to determine the proper timing.
  • General Knowledge of Gray Codes: Gray codes are well-known in digital electronics for their property that only a single bit changes between successive codewords. This makes them inherently robust for timing measurements where small skews might otherwise lead to erroneous readings, a property recognized by the '393 patent itself. A PHOSITA would understand the utility of Gray codes for reliable state encoding, especially in asynchronous or delay-sensitive contexts.
  • General Knowledge of Lookup Tables: Lookup tables are standard mechanisms in digital design for mapping a set of input values (e.g., a sampled pattern) to corresponding output values (e.g., a delay setting or control parameter).

• Motivation to Combine:
  A PHOSITA, facing the "significant amount of time during system initialization" required by the iterative "Programmable GATEON" approach for read data training, would be strongly motivated to devise a faster and more efficient method. Combining the concept of read data training (from LSI Logic) with the robust properties of Gray codes (general knowledge) would naturally lead to using a Gray code as the initialization sequence to reliably capture the system's state relative to the read command in a single attempt. Sampling this known sequence at a predetermined time to get a "snapshot" and then using a lookup table to directly determine the optimal DQS enable timing (instead of iterative searching) would be an obvious improvement to reduce initialization time and complexity. The idea of characterizing a system's delay by transmitting a known pattern, capturing a snapshot of the received pattern relative to a reference, and mapping this snapshot to a delay value is a fundamental diagnostic technique.

2. Drift Detection and Compensation (Claim 13, and related aspects)

Claim 13 teaches on an ongoing basis determining if there is clock drift, and if so, updating the read delay. The patent describes a specific drift detector circuit in FIG. 9A, using D flip-flops clocked by DQS and sampling 0° and 90° phases of a master clock.

• Prior Art Teachings:

  • LSI Logic "Programmable GATEON": Explicitly identifies a major disadvantage as its inability to "accommodate timing drift during operation." This highlights the recognized problem of drift.
  • General Knowledge of Phase Detection: The concept of detecting phase differences or drift between two clock signals using multiple phases of a reference clock is a fundamental technique in digital circuit design, commonly implemented in Phase-Locked Loops (PLLs) and Delay-Locked Loops (DLLs) for clock synchronization. Using 0° and 90° phases to detect a quarter-cycle (90°) phase shift is a basic and well-known method of phase detection.

• Motivation to Combine:
  Given that "Programmable GATEON" cannot accommodate timing drift, a PHOSITA would be motivated to add a mechanism for drift detection and compensation. The problem of timing drift due to environmental factors (temperature, voltage) is well-understood. Applying known phase detection techniques, such as latching multiple phases (e.g., 0° and 90°) of a stable master clock with the potentially drifting DQS signal (as the input clock) to identify phase changes, would be an obvious solution to the identified problem. Once drift is detected, the logical next step is to update the previously determined DQS enable timing to compensate, thereby maintaining robust data capture.

3. Specific DQS Enable Gating Circuit (Claims 21-23)

Claim 21 details a DQS enable circuit comprising an input for DQS, an output for a gated DQS, a multiplexer, and a select input generator circuit (including D flip-flops, an AND gate, and an SR flip-flop clocked by the gated DQS) that sets the select input to enable DQS upon activation of a DQS enable signal and deselects it upon activation of a DQS disable signal and following a next edge of the data strobe signal. Claim 22 adds producing a gated inverse DQS. Claim 23 describes a circuit for selecting between DDR1 and DDR2 modes.

• Prior Art Teachings:

  • Schoenfeld '336 (and general DDR SDRAM knowledge): Discloses the use of a bidirectional data strobe signal in DDR SDRAM. The background of the '393 patent emphasizes the necessity to gate the DQS clock input to prevent "spurious clock edges created by a tri-stated clock input level from triggering internal data capture."
  • LSI Logic (GATEON): Reinforces the concept of enabling the DQS read strobe using a control signal (GATEON).
  • General Digital Circuit Design Principles: Glitch-free clock gating is a fundamental concern in synchronous digital design. Common techniques involve synchronizing control signals to the clock being gated and using logic (such as SR flip-flops or other combinational logic with edge synchronization) to ensure that the clock is enabled/disabled cleanly without introducing partial pulses or metastability. The use of multiplexers for signal selection and for providing backward compatibility (e.g., between DDR1 and DDR2 modes, as described for circuit 180 in FIG. 8A) is also a standard engineering practice.

• Motivation to Combine:
  A PHOSITA tasked with designing a DQS enable circuit for a DDR memory controller would be motivated to ensure robust and glitch-free operation, as required for reliable data capture. Combining the functional requirement of DQS gating (from the DDR standard and LSI Logic's GATEON concept) with standard digital circuit design principles for clock gating would lead to the design of a circuit similar to that described in Claim 21. The specific arrangement of D flip-flops, an AND gate, and an SR flip-flop clocked by the gated DQS is a well-known and conventional approach to synchronize enable/disable signals and produce a glitch-free gated clock output. Extending this to gate an inverse DQS (Claim 22) when both are present (e.g., in DDR2) or to generate an inverse DQS for backward compatibility (Claim 23) using multiplexers would be obvious design choices for a PHOSITA implementing a flexible DDR controller.

4. Clock Domain Crossing for Data Re-timing (Claim 16, 19)

Claim 16 describes re-timing read data signals to an RTL clock. Claim 19 includes a circuit for re-timing data signals to a main clock.

• Prior Art Teachings:

  • General DDR Memory System Knowledge: The '393 patent explicitly identifies "how to transfer data clocked in with DQS to the system clock domain when the phase between the DQS clock and master system clock CLK can be completely arbitrary" as a "third problem." This describes a classic clock domain crossing (CDC) scenario.
  • General Knowledge of Clock Domain Crossing (CDC) Techniques: Solutions for CDC are widely known and documented in digital design. These include using asynchronous FIFOs, multi-flop synchronizers, or sampling data with multiple phases of the destination clock to determine the best sampling point. The patent describes circuit 85 (FIG. 4) that samples DQ0 and DQ1 with 0° and 180° clock phases and selects between them with a multiplexer to "produce outputs... that are re-timed to be synchronous with the 0° clock."

• Motivation to Combine:
  A PHOSITA designing a memory controller would be motivated to reliably transfer data from the memory's DQS clock domain to the controller's internal system clock (RTL clock) domain, especially when their phases are arbitrary. This is a recognized problem (the "third problem" identified by the '393 patent). Applying known CDC techniques, such as capturing data with multiple phases of the destination clock (e.g., 0° and 180° from the master DLL, which are explicitly stated to be available) and selecting the appropriately timed sample, would be an obvious engineering solution to achieve robust clock domain crossing.

In conclusion, the innovations claimed in US7685393, while providing specific implementations, represent combinations of known techniques and solutions to identified problems within the context of DDR memory controllers. A PHOSITA, aiming to overcome the limitations of existing read data training and DQS gating methods (as described in prior art like the LSI Logic document) and to address common challenges in high-speed synchronous memory interfaces (like timing drift and clock domain crossing), would have been motivated to combine these known elements in the manner claimed.