Obviousness

The obviousness of US Patent 7,632,751 under 35 U.S.C. § 103 can be analyzed by considering the distinctions between the claimed invention and the prior art, the motivation for a person having ordinary skill in the art (PHOSITA) to combine or modify prior art teachings, and any secondary considerations.

Conventional Prior Art as Described in US7632751:
The patent itself extensively describes a "conventional multilevel interconnection structure" and its associated drawbacks, explicitly referencing Japanese Unexamined Patent Publication (Kokai) No. 2000-331991. This conventional structure, illustrated in FIGS. 19B and 19C of the patent, includes:

• A first (lower) interconnect (2) buried in an insulating film (1).
• A SiN film (3), a SiO2 film (4), and an FSG film (5) stacked over the lower interconnect.
• A via hole (6) formed through the SiO2 and SiN films to reach the first interconnect.
• An interconnect trench (7) formed in the FSG film to reach the via hole.
• A barrier film (8) and a Cu film (9) filling the via hole and trench, forming a via (10) and a second (upper) interconnect (11).
• A SiN film (12) on the FSG film and the second interconnect.

The Known Problem in the Prior Art:
US7632751 clearly identifies a critical problem with this conventional structure: "A large number of vacancies are present in the Cu film 9 deposited by plating. When the multilevel interconnection structure is held at high temperature, these vacancies move along the gradient of stress." Specifically, it notes that vacancies flow from the larger volume second interconnect (11) into the smaller via (10), leading to "plastic deformation" and the creation of a "void 13" in the via hole (as shown in FIG. 20A). This void breaks the electrical connection, causing device malfunction.

Motivation for a PHOSITA to Combine/Modify:
A PHOSITA in the field of semiconductor device fabrication, aware of the conventional multilevel interconnection structure (as described based on JP 2000-331991) and the explicitly stated problem of vacancy-induced void formation and device malfunction, would be highly motivated to find solutions that improve reliability by suppressing vacancy movement or void occurrence. The stated objective of US7632751 is precisely "to achieve a highly-reliable multilevel interconnection structure which does not cause malfunction even when the structure is held at high temperature." The underlying technical idea is to reduce the stress gradient and suppress vacancy movement.

The combination of the conventional interconnect structure (JP 2000-331991) with general knowledge in semiconductor processing regarding stress management, electromigration, and the use of dummy features or diffusion barriers would render the claims of US7632751 obvious.

Obviousness Analysis of Independent Claims:

1. Independent Claim 1 (First Interconnection Structure) and its related Methods (Claims 4 & 5):

   • Distinction: The inclusion of at least one "dummy via" connected to the upper interconnect, where its bottom is located in the second insulating film (Claim 1) or formed above the upper interconnect (Claim 5 method). The dummy via is insulated from the lower interconnect and does not form part of a closed circuit.
   • Motivation: Faced with the known problem of vacancies flowing into the functional via and causing voids in the conventional structure, a PHOSITA would seek ways to divert or absorb these vacancies. The patent explicitly states that the dummy via "reduces the stress gradient from the upper interconnect to the via" and divides vacancies to flow into both the functional and dummy vias. Dummy structures are commonly used in semiconductor manufacturing for various purposes (e.g., controlling material density during chemical-mechanical planarization (CMP), relieving stress). Applying the concept of a non-functional (dummy) feature to act as a preferential sink for vacancies, thereby protecting the active via, is an obvious adaptation of known design principles to solve a known problem. The specific placement of the dummy via's bottom in the second insulating film (making it deeper than the functional via) is described in the patent as increasing the stress gradient and making it more effective at attracting vacancies, which is a predictable optimization for achieving the desired function. The methods of forming these dummy vias (Claims 4 and 5) involve standard lithography and etching steps, simply requiring modification of mask patterns, which is routine for a PHOSITA.

2. Independent Claim 2 (Second Interconnection Structure) and its related Method (Claim 6):

   • Distinction: The presence of at least one "insulating slit" formed within the upper interconnect.
   • Motivation: A PHOSITA, understanding that vacancy flow in the conventional structure is driven by stress gradients and material diffusion, would be motivated to introduce a barrier. The patent clarifies that the insulating slit reduces the stress gradient and acts as a barrier against the movement of atoms or vacancies. Insulating barriers (e.g., dielectric layers, liners) within conductive lines are fundamental elements in semiconductor design to provide isolation and sometimes affect diffusion. Introducing such a slit into the upper interconnect of the conventional structure, particularly near the functional via, to disrupt vacancy pathways or modify local stress fields to prevent void formation, would be an obvious solution to the known problem. The method of forming the insulating slit (Claim 6) by leaving part of the insulating film during trench formation is a direct application of dual damascene processing with a modified mask, a routine design choice.

3. Independent Claim 3 (Third Interconnection Structure) and its related Method (Claim 7):

   • Distinction: The upper interconnect is divided into a wider first portion and a narrower second portion (with the via connected to the narrow portion), and a "dummy portion" is provided such that its distance to the branch point between the wide and narrow portions is smaller than its distance to the opposite edge of the narrow portion.
   • Motivation: The conventional structure shown in FIG. 19C already features a wide upper interconnect (11) connected to a narrower lower interconnect (2) via a via (10). The patent explicitly notes that "the volume of the second interconnect 11 is much greater than that of the via 10, so that a large number of vacancies flow from the second interconnect 11 into the via 10." This identifies transitions from wide to narrow interconnects as particular problem areas for vacancy flow. A PHOSITA, recognizing this specific weakness in the conventional structure, would be motivated to strategically place a vacancy sink (a "dummy portion," similar in concept to a dummy via) at or near this critical branch point to intercept vacancies early. The placement closer to the branch point is an obvious optimization to maximize its effectiveness in capturing vacancies before they reach the functional via. The method for forming this structure (Claim 7) involves forming the interconnect trench with wide and narrow sections and a recess for the dummy portion, which is a straightforward design modification using established patterning and deposition techniques.

In conclusion, all independent claims of US7632751, whether describing structures with dummy vias or insulating slits, or specific configurations of these features, address a known problem (via voiding due to vacancy migration) in a conventional semiconductor interconnect structure (JP 2000-331991). The proposed solutions involve well-understood principles of stress management and diffusion barriers in semiconductor fabrication, applied through routine design modifications and manufacturing techniques. A PHOSITA would have been motivated to combine the teachings of the conventional prior art with general knowledge in the field to arrive at the claimed inventions to improve device reliability.