US 7571266

I'll search for authoritative information on US 7,571,266, including any CAFC 2026 docket activity.

Let me run more targeted searches on the patent and its owner.

US Patent 7,571,266 — Summary

Source (authoritative): Google Patents, https://patents.google.com/patent/US7571266/en (fetched 2026-09-24). All bibliographic data below is drawn from that record; where a search returned nothing, I say so explicitly.

Bibliographic data

Assignment chain (from the "Legal Events" section):

• 2006-02-06 (eff. 2006-01-30): Assignment to Cornice, Inc. (assignor: Carlson, Lance R.).
• 2006-11-06 (eff. 2006-11-03): Security agreement to VantagePoint Venture Partners IV, L.P., as collateral agent (assignor Cornice, Inc.).
• 2007-08-01 (eff. 2007-06-07): Assignment from Hercules Technology Growth Capital, Inc. to Benhov GmbH, LLC (Delaware).
• 2007-11-14 (eff. 2005-11-30 as listed): Assignment from Cornice, Inc. to Hercules Technology Growth Capital, Inc.

Abstract (verbatim)

A computerized system is described (i) which includes an interface connected with a peripheral device and (ii) which is incapable of dynamically extending bus cycle timing if required by the peripheral device to carry out a particular current operation. This computerized system includes a given peripheral device which, during normal operation of the device, can require an extension of bus cycle timing to carry out the current operation. This device generates a specific signal when the extension is required. The device is connected with the interface of the computerized system and the system is configured to cause the system (i) to recognize the specific signal and (ii) to instruct the peripheral device to retry the current operation responsive to the specific signal. In a particular embodiment, the peripheral device is a disk drive having an ATA interface and the specific signal generated by the disk drive is an IORDY signal.

Plain-language overview of the independent claims

The patent has 23 claims and six independent claims (1, 7, 13, 14, 15, 19). The core idea is consistent across all of them: instead of making a non-ATA host actually honor the IORDY "wait" line, the host simply detects IORDY de-assertion and re-sends (retries) the operation, because genuine de-assertions are rare so the retry almost always succeeds.

Claim 1 — Method (the base claim). In a computerized system that (i) has an interface for a peripheral and (ii) cannot dynamically extend bus-cycle timing when the peripheral needs it: (a) provide a peripheral device inside the system that sometimes needs extra bus-cycle time to complete the current operation and that emits a specific signal when that extension is needed; and (b) wire it so that the peripheral's output carrying that specific signal goes to an interrupt input of the interface, and configure the system to recognize that signal via the interrupt input and, in response, tell the peripheral to retry the current operation.

Claim 7 — System. The apparatus counterpart: a host with an interface for a peripheral that cannot extend bus-cycle timing; a peripheral that under certain conditions needs extended timing and generates a specific signal when it does; the peripheral connected so its specific-signal output goes to an interrupt input of the interface, the system recognizing the signal through that interrupt input and instructing the peripheral to retry the operation.

Claim 13 — Method (host-side framing). Substantively the same subject matter as claim 1 but phrased as: provide such a host; provide such a peripheral; connect the interface so the specific-signal output goes to an interrupt input of the interface, causing the system to recognize the signal and instruct the peripheral to retry.

Claim 14 — System (interface-centric framing). Same concept expressed around the interface: a host whose interface is adapted for connection to such a peripheral, the interface configured so the peripheral's specific-signal output connects to an interrupt input of the interface, causing recognition of the signal and a retry instruction. (Note it is drafted with "said peripheral device" language even though the peripheral is introduced as the device the interface is adapted to connect to.)

Claim 15 — Computer system (bus-period framing, added by the later-filed claims). A host bus; a processor that sends operation requests and receives responses synchronously with a fixed bus-cycle period; a peripheral whose response time is variable, with some responses taking longer than the fixed period, and which sends a first signal to the processor for those overlong responses; the processor has an interrupt to receive the first signal and is programmed to respond by instructing the peripheral to repeat the responses that exceeded the fixed bus-cycle period.

Claim 19 — Method (bus-period framing). Couple a variable-response-time peripheral and a fixed-bus-cycle-time host to a host bus; send an operation request; the peripheral produces a successful response; if that successful response took longer than the fixed bus-cycle time, send a first signal to the host; the host responds to the first signal by instructing the peripheral to respond again to the same operation request — expressly "notwithstanding successful response by the peripheral device to the operation request."

Dependent claims of note (not independent, summarized): Claims 2–6 depend ultimately on claim 1 (disk drive; ATA drive into a non-ATA interface; IORDY as the specific signal used in PIO mode; negative-edge-sensitive interrupt input). Claims 8–12 mirror these on the system of claim 7. Claims 16–18 depend on claim 15 (ATA peripheral / non-ATA processor; first signal = de-assertion of IORDY; IORDY coupled to a processor interrupt). Claims 20–22 depend on claim 19 (same ATA/IORDY/interrupt limitations). Claim 23 depends on claim 22 and adds the READ SECTORS workflow: peripheral signals data-ready, host issues multiple read requests, peripheral returns data words, host monitors IORDY, and if IORDY de-asserts during any read request, the host resends the READ SECTORS command.

Prior art cited on the face of the patent (7 references)

US4845614 (Hitachi, "Microprocessor for retrying data transfer"), US4989113 (TI), US5490287 (Canon), US5625847 (Toshiba, high-speed ISA bus), US5732250 (Intel, multi-function microprocessor wait state mechanism using external control line), US5850555 (AMD, validating interrupts), US6477596 (Sanyo, delaying activation of a bus cycle). Non-patent citations include Intel PXA27x application note and developer's manual (2005/2006), a Maxtor ATA-5 (ATA/ATAPI-5) document (2000), and the QuickLogic QuickIDE Bridge User Manual (2006).

CAFC 2026 docket check — result: no match found

I searched for patent number 7571266 and for CAFC 2026 activity, including the Federal Circuit's scheduled-cases listing for June 2026. I found no CAFC 2026 docket, appeal, or scheduled argument naming US 7,571,266.

Related facts surfaced, but they are not this patent and should not be attributed to it:

• The only Benhov-related Federal Circuit appeal I could surface is 19-1053, In re Benhov GmbH / K/S HIMPP (2019) — that appears tied to a different Benhov patent (the K/S HIMPP IPR activity concerned US 8,768,147), not US 7,571,266.
• Benhov's PTAB activity I found (IPR2017-00930 / IPR2017-00934, 2017) likewise relates to other Benhov patents (e.g., 8,768,147), not 7571266.

Uncertainty / caveats: (1) My web-search access returned no direct USPTO PatentCenter or full-text CAFC docket page for this specific number, so I cannot independently confirm current USPTO status from PatentCenter beyond the Google Patents record; (2) absence of a CAFC 2026 hit may reflect limitations in what my searches indexed rather than proof that no such proceeding exists — treat the "no CAFC 2026 docket" finding as negative search evidence, not affirmative confirmation. The bibliographic data and claim text above rest on the authoritative Google Patents full text supplied to me.

I'll search for litigation involving US patent 7571266.

Let me search more specifically for litigation records.

Summary: No litigation found involving U.S. Patent No. 7,571,266

I conducted multiple targeted searches (Google Patents, litigation-aggregator content, PTAB/CAFC materials, and NPE/ownership trails) and found no district court litigation, ITC action, or PTAB proceeding in which U.S. Patent No. 7,571,266 ("Peripheral device in a computerized system and method") was the patent-in-suit or was otherwise challenged.

Because no case exists to report, I cannot provide plaintiff/defendant/jurisdiction/case number/filing date/outcome — no such record was located. Details of what I did and did not find are below.

What the patent's own record shows

• Patent: US 7,571,266 B2; App. No. 11/348,079; filed 2006‑02‑06; granted 2009‑08‑04; inventor Lance R. Carlson; pub. US20070239908A1.
• Ownership trail (relevant to who could have asserted it): Individual → Cornice, Inc. (assignment recorded 2006‑02‑06) → security interest to VantagePoint Venture Partners IV, L.P. (2006‑11‑06) → assignment to Hercules Technology Growth Capital, Inc. (recorded 2007‑11‑14) → assignment to Benhov GmbH, LLC (recorded 2007‑08‑01, effective 2007‑06‑07). Current listed assignees: Cornice Inc. / Benhov GmbH LLC.
• Status: Active; adjusted expiration 2026‑08‑25 (i.e., it is at/near the end of its term as of today, April 26, 2026).
• The Google Patents record shows no "Litigation" section, and the only third‑party citations are later patents that cite it (e.g., US20090049209A1 / US7739440B2 to Texas Instruments; US20140189162A1 / US8954632B2 to Silicon Laboratories) — these are citations, not litigation.

Apparent source of confusion (things that look like "7571266" but are not)

My searches surfaced several proceedings against the patent's owner, Benhov GmbH, LLC, but the patents at issue are different patents — do not attribute these to the '266 patent:

• K/S HIMPP v. Benhov GmbH, LLC, IPR2017‑00930 (PTAB, filed 2017‑02‑21; terminated 2018‑08‑10) — concerns a hearing‑aid/audio patent (inventors Michael A. Vaudrey and William R. Saunders), not the '266 ATA/IORDY patent.
• K/S HIMPP v. Benhov GmbH, LLC, IPR2017‑00934 — patent 8,768,147 ("Use of Voice‑to‑Remaining Audio (VRA) in Consumer Applications").
• Benhov GmbH, LLC v. K/S HIMPP, Nos. 2019‑1053 / 2019‑1110 (Fed. Cir.) — appeals arising from those HIMPP IPRs; No. 2019‑1110 was dismissed (order Sept. 26, 2019).
• Other Benhov‑owned patents seen in the record include US 9,344,482 and RE47,053.
• The '126 patent decisions/phrases that appear in search results (e.g., Agere v. Atmel, and CCGroup/Optum) refer to entirely different patents numbered '126, not US 7,571,266.

Confidence and caveats

• I am highly confident there is no well‑known or indexed litigation naming US 7,571,266 — it is a short‑lived peripheral‑interface patent from a defunct startup (Cornice) that was assigned into the Benhov holding entity, and I found no assertion activity on it.
• I could not exhaustively query paywalled dockets (PACER, Docket Navigator, Lex Machina, RPX Insight) or the Unified Patents litigation portal directly in this session. It remains possible (though I found no evidence) that the '266 patent appears in a complaint as one of many patents‑in‑suit, or in a case that was never indexed. If you need a definitive, docket‑verified negative, the authoritative check is a Docket Navigator / Lex Machina "Patent" search on 7,571,266 and a PACER/CAFC party search on "Benhov GmbH, LLC."

Bottom line: Based on all available sources I could reach, no litigation is known involving U.S. Patent No. 7,571,266. The Benhov/HIMPP proceedings that appear in searches concern other Benhov‑owned patents and should not be reported as litigation on the '266 patent.

I'll verify the ODP default with targeted searches before drafting.

Let me run additional targeted checks on the patent number, owner, and any assertion history.

Verification note before the analysis

The canonical structured block (USPTO ODP, "PTAB proceedings on file") returns zero AIA trial proceedings for US 7,571,266. I ran four independent web searches (patent number, patent number with "IPR"/"PTAB", owner/troll-name searches, and docket-aggregator searches) and found no IPR, PGR, or CBM naming this patent. The hits that surface a "'126 patent" in PTAB decisions refer to a different patent (a two-phase heat-exchanger patent, e.g. proceedings citing Ex. 1001 with an "air-to-fluid heat exchanger"). I am not importing those into this analysis.

Also flagging: the ODP block lists an adjusted expiration of 2026-08-25 and today's date is 2026-10-01 — i.e., the listed term-end date is already in the past. The "Active" legal-status label appears to lag reality. Verify in USPTO Patent Center before relying on it, but the practical read is that the patent term has run.

Proceedings overview

Total AIA trial proceedings on file: 0 — 0 active, 0 with claims invalidated, 0 with claims sustained, 0 settled, 0 instituted, 0 institution-denied. The patent has never been challenged at the PTAB, so the bottom-line defensive posture is not "hardened by IPR" — it is untested but also unrestrained: there is no § 315(e)(2) estoppel against anyone, the full prior-art space is available to you, and the patent's own listed term appears to have expired, which strips the patent owner of any injunctive leverage.

No proceedings to enumerate

There are no proceeding numbers, petitioners, panels, institution decisions, Final Written Decisions, settlements, or appeals to report for US 7,571,266. Per the operating rule against inventing proceeding numbers, I am listing none rather than presenting anything as "on file."

Strategic summary

Claim status: everything is UNTESTED. Claims 1–23 were never subjected to an AIA trial. Independent claims are claim 1 (method), claim 7 (system), claim 13 (method), claim 14 (system), claim 15 (computer system), and claim 19 (method); the remainder are dependents (2–6, 8–12, 16–18, 20–23). There are no canceled claims, no confirmed claims, and no narrowed claims — the patent's scope is exactly as issued, subject to a certificate of correction entered 2009-10-27 (per the ODP legal events). That correction means the claim text as printed differs from the text as corrected; pull the corrected claims from Patent Center / PTAB E2E before building any chart. The patent's core insight is narrow and behavioral: an ATA drive de-asserts IORDY, that de-assertion is routed to a host interrupt input (negative-edge-sensitive per claim 6/12), and the host responds by retrying the operation rather than extending the bus cycle (claims 1, 7, 13, 14, 15, 19, 23).

Estoppel landscape: none. Because no IPR/PGR was ever instituted, § 315(e)(2) estoppel has never attached to anyone, and neither has the § 325(e)(2) analog. A defendant currently facing assertion (or an indemnitor standing behind one) can file an IPR on any § 102/§ 103 ground, and can run the same art in district court, without any estoppel risk from a prior proceeding. The only bars are ordinary ones: the § 315(b) one-year clock from service of a complaint alleging infringement, and § 315(a)(1) if you first filed a DJ action of invalidity. Note also that if the patent is in fact expired as of 2026-08-25, an IPR on an expired patent is still permissible but the Board applies a Phillips-like construction and the practical payoff is limited to defeating the § 286 six-year back-damages tail.

Pattern signals: absent. There is no repeat petitioner, no serial-petition/General Plastic dynamic, and no defensive aggregator (no Unified Patents or similar) in the record. The assignment chain runs Individual → Cornice, Inc. (2006) → Hercules Technology Growth Capital, Inc. (recorded 2007) → Benhov GmbH, LLC (recorded 2007), with ODP listing current assignees as both Cornice Inc. and Benhov GmbH LLC. Benhov is a known monetization vehicle, yet this patent — a 2006 filing that has been in force since 2009 — attracted zero PTAB challenges in ~17 years. The absence of even one IPR is itself informative: either the patent was never asserted in a way that justified the ~$500K–$1M cost of an IPR, or targets chose cheaper routes (design-around, license, or invalidity contentions in litigation). Do not read zero IPRs as "validity is confirmed"; read it as "nobody has litigated this to the Board yet."

One current-practice caveat worth pricing in. If a petition is filed now, discretionary denial is a live risk. Under the USPTO's March 26, 2025 bifurcated institution process, "settled expectations of the parties, such as the length of time the claims have been in force" is an express discretionary consideration, and secondary reporting (DeFosse/Smith/Kasai, Aug. 29, 2025) indicates a de facto ~six-year threshold has driven a high rate of discretionary denials. A patent in force since 2009 and now expired sits at the extreme end of that spectrum, so a fresh IPR petition should be paired with a non-IPR strategy. (This paragraph rests on secondary sources I did not verify against the ODP block — treat as context, not established fact for this docket.)

Recommended next steps

1. Lead with expiry, verify it today. The ODP block's adjusted expiration (2026-08-25) predates today (2026-10-01). Confirm in Patent Center and via the fee/legal-status history: maintenance fees were paid at year 4 (2013-01-25), year 8 (2017-01-26), and year 12 (2020-09-28), and no lapse event appears in the ODP legal events. If the term has run, no injunction is available; exposure is capped at the § 286 six-year back-damages window (roughly 2020-10-01 forward to expiry), plus any pre-suit notice-driven enhancement argument.
2. Get the corrected claims. A certificate of correction issued 2009-10-27 (ODP legal events). Obtain the corrected claim set from PTAB E2E or Patent Center before serving invalidity contentions or building a non-infringement chart — the printed patent text is not reliable here.
3. Mine the intrinsic record's art of record, which nobody has tested. The patent cites seven US references — US4845614 (Hitachi, microprocessor for retrying data transfer — directly on the retry concept), US4989113 (TI, DMA transfer control), US5490287 (Canon), US5625847 (Toshiba, high-speed ISA bus control changing command cycle execution speed), US5732250 (Intel, multi-function microprocessor wait-state mechanism using an external control line — directly on the wait/ready-line function), US5850555 (AMD, validating interrupts before presentation to a CPU), US6477596 (Sanyo, delaying activation of a bus cycle) — plus four NPL items: Intel's Oct. 2005 PXA27x-to-HDD-via-VLIO application note, the Intel PXA27x Developer's Manual (Jan. 2006), the Maxtor ATA-5 spec (Feb. 2000), and the QuickLogic QuickIDE Bridge User Manual (2006). The Intel VLIO app note and the QuickLogic QuickIDE bridge manual describe exactly the undertaking at the heart of claims 1/7/13/14 — connecting an ATA HDD to a non-ATA memory interface. These are the highest-value § 102/§ 103 starting points, and with no IPR on file you can use them in either forum.
4. Preserve the IPR option against § 315(b). If you have been served with a complaint asserting '266, calendar the one-year § 315(b) bar immediately and decide file-or-forgo before it lapses; there is no existing estoppel to discourage filing.
5. No FWD to cite. There is no Final Written Decision, institution decision, or Federal Circuit opinion to link for this patent. Any representation to the contrary — from opposing counsel or an assertion letter — that claims have been canceled or sustained at the PTAB would be false.

I'll start by pulling the assignment records and any public litigation/NPE context. Note that the patent text you supplied already contains Google Patents' legal-events reconstruction, which I'll treat as the authoritative baseline and then cross-check.

Let me dig deeper on Benhov GmbH's identity and the Cornice/Hercules chain.

Ownership Reconstruction — US 7,571,266 B2

Patent: "Peripheral device in a computerized system and method" (App. 11/348,079, filed 2006‑02‑06; granted 2009‑08‑04; assignee of record per Google Patents: Cornice Inc / Benhov GmbH LLC).

Data caveat up front: the four assignment events below are reconstructed from the Google Patents legal‑events table (which mirrors USPTO assignment data) and carry reel/frame numbers. The USPTO Assignment Center correspondent-of-record field could not be retrieved in this session — the Assignment Center is a JS/CAPTCHA-gated app and the reel/frame document images were not accessible. I therefore do not have verified correspondent names for this chain and will say so at each entry rather than guess. There is also a metadata inconsistency worth flagging: Google Patents lists "Original Assignee: Individual" in its header block, yet the first recorded instrument transfers Carlson's rights to Cornice, Inc. I treat the assignment record as controlling.

Inventors

• Lance R. Carlson — sole named inventor. Employer at filing: Cornice, Inc. (Longmont, Colorado), established by the first recorded assignment, executed 2006‑01‑30, in which Carlson assigns to CORNICE, INC. (reel 017548/0551). No other inventor appears on the face of the patent.

Pattern note: with a single inventor there is no "all inventors departing" pattern to measure, and I found no evidence of Carlson's post‑2006 whereabouts — I will not speculate. The salient lifecycle fact is institutional rather than personal: the employer (Cornice) collapsed in 2007, roughly 18 months after this application was filed, and the patent left Cornice through the lender/collateral chain described below while prosecution was still pending (the application did not publish until 2007‑10‑11, after the transfers had begun).

Original assignee

Cornice, Inc. / Cornice LLC — Longmont, Colorado. A venture‑backed 1‑inch microdrive maker ("Storage Element" / SE product line), founded August 2000 by Kevin Magenis (ex‑Maxtor) and Curt Bruner (ex‑Quantum). It shipped a product embodying its storage technology — the 1.5 GB 1‑inch drive began shipping June 2003, with customers including Thomson (RCA Lyra), iRiver, Rio (Nitrus), and Digitalway, and a follow‑on 2 GB model shown at CES 2004. Primary line of business: miniature rotating magnetic storage for portable consumer electronics (MP3 players, DVRs, etc.).

Financing: ~$81.7M raised by early 2004 (a $51M round in January 2004), with investors including VantagePoint Venture Partners, CIBC Capital Partners, Nokia Venture Partners, BA Venture Partners, and GIC Special Investments.

Status: out of business / bankrupt (2007). Multiple defunct‑HDD compilations list "Cornice LLC – bankrupt in 2007," and company‑profile aggregators list Cornice status as "Out of Business" at 1951 S. Fordham St., Longmont, CO. The patent's departure from Cornice in 2007 is contemporaneous with that failure.

Assignment timeline

• 2006‑01‑30 (executed) / recorded 2006‑02‑06 — Reel 017548/0551

  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS INTEREST)
  • Assignor: Carlson, Lance R.
  • Assignee: Cornice, Inc. (Colorado)
  • Correspondent: not retrieved (Assignment Center record not accessible this session; Google Patents legal events omit the correspondent field)
  • Context: initial inventor-to-company assignment — the founding transfer that makes Cornice the original assignee.

• 2006‑11‑03 (executed) / recorded 2006‑11‑06 — Reel 018480/0564

  • Conveyance: Security Agreement
  • Assignor: Cornice, Inc.
  • Assignee: VantagePoint Venture Partners IV, L.P., as Collateral Agent
  • Correspondent: not retrieved (record not accessible; no correspondent captured in available event data)
  • Context: securitization — Cornice pledges its IP to its lead VC acting as collateral agent, a classic venture‑debt/lien perfecting step.

• 2007‑06‑07 (executed) / recorded 2007‑08‑01 — Reel 019628/0193

  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS INTEREST)
  • Assignor: Hercules Technology Growth Capital, Inc.
  • Assignee: Benhov GmbH, LLC (Delaware; Wilmington, DE)
  • Correspondent: not retrieved (record not accessible). Adjacent (non‑assignment) data point: later Benhov‑owned patents list prosecution counsel Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. as attorney of record (e.g., US RE47,053 and US 9,344,482) — a recurring firm across the Benhov family, but that is prosecution counsel, not the recorded assignment correspondent, so it is not a finding for this chain.
  • Context: transfer out of the lender to a holding/aggregation company — the venture‑debt lender's collateral interest is monetized to an IP holding LLC; effectively the distressed‑asset disposition of Cornice's patent.

• 2005‑11‑30 (executed) / recorded 2007‑11‑14 — Reel 020113/0728

  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS INTEREST)
  • Assignor: Cornice, Inc.
  • Assignee: Hercules Technology Growth Capital, Inc. (California)
  • Correspondent: not retrieved (record not accessible)
  • Context: lender taking title to collateral — note the out-of-order recording: this instrument is dated 2005‑11‑30 and was recorded 2007‑11‑14, i.e. after the downstream Hercules→Benhov assignment was already recorded on 2007‑08‑01. That sequencing is a title‑repair signature of a distressed‑debt workout, not an ordinary corporate transfer.

Chain reading: Carlson → Cornice (2006) → security interest to VantagePoint as collateral agent (2006) → title to Hercules Technology Growth Capital (venture‑debt lender; instrument dated 2005, recorded 2007) → relinquished to Benhov GmbH, LLC (2007). The patent never passed through a Chapter 7/11 sale docket that I could locate; it left the estate via the secured‑lender route. The "2026‑08‑25 adjusted expiration" and the 2009‑10‑27 certificate of correction in the file are not assignments.

Note on missing records: I found no recorded post‑2007 assignment, so Benhov GmbH, LLC remains the current assignee of record (consistent with Google Patents' "Current Assignee" field listing Benhov).

Timeline diagram

timeline
    title Ownership of US 7571266
    2006 : Filed by Cornice Inc
         : Carlson assigns rights to Cornice
         : VantagePoint security agreement recorded
    2007 : Cornice fails
         : Benhov GmbH LLC takes rights from Hercules
         : Hercules title recorded out of order
    2009 : Patent granted Aug 4
    2026 : Adjusted expiration Aug 25

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT. Patent moves from an operating drive manufacturer (Cornice, shipping a real product since 2003) to Benhov GmbH, LLC, a Wilmington, Delaware holding entity with no product line, via the lender. Evidence: reels 020113/0728 (Cornice→Hercules) and 019628/0193 (Hercules→Benhov), both 2007. Benhov's recorded address in related filings is 2711 Centerville Road, Suite 400, Wilmington, DE 19808 (WO2008019347), a commercial registered‑office address; portfolio aggregators attribute ~240 patents to Benhov spanning wholly unrelated technology areas (disk drives, hearing aids, printing‑press inspection, flash memory), which is the signature of a buying vehicle rather than an operating company.

2. Known asserter in the chain — UNCLEAR (leaning present). Benhov GmbH, LLC does not appear on the enumerated lists (Acacia, Marathon, IV, IPNav, Wi‑LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation, Spangenberg). However, it appears as patent owner in an active PTAB proceeding — K/S HIMPP v. Benhov GmbH, LLC, IPR2017‑00934, filed 2017‑02‑21, on US 8,768,147 (hearing‑aid/VRA art) — which is assertion-adjacent conduct. Separately, Unified Patents' portal lists "Parent Company: Intellectual Ventures LLC" for patents whose Current Assignee is Benhov GmbH LLC. I flag that as a corroborating source, not a verified ownership fact.

3. Repeat correspondent across the chain — UNRETRIEVED / UNCLEAR. I could not obtain the correspondent of record for reels 017548/0551, 018480/0564, 019628/0193, or 020113/0728, so I cannot make or refute a recurrence finding. This is the single highest‑value gap in this reconstruction and the field to pull first from Assignment Center (search patent 7,571,266 → reel 019628/0193 is the key link, since it is the Benhov acquisition).

4. Cascading transfers — PRESENT. Three recorded instruments inside roughly 21 months (2006‑11‑06 → 2007‑08‑01 → 2007‑11‑14) across a VC collateral agent, a venture‑debt lender, and a Delaware holding LLC. The out‑of‑order recording (Benhov purchase recorded 2007‑08‑01 before the Cornice→Hercules title record of 2007‑11‑14) reinforces that these were chain‑repair filings, not arm's‑length operating transfers.

5. Pre-litigation transfer — UNCLEAR / not established. I surfaced no infringement suit naming US 7,571,266, so the 6‑month look‑back cannot be tested. Do not assume assertion of this patent from Benhov's IPR activity on other patents.

6. Bankruptcy fire‑sale — PRESENT. Cornice is listed as bankrupt in 2007 by multiple defunct‑HDD compilations and "Out of Business" by company‑profile aggregators. The 2007 instruments (reels 019628/0193, 020113/0728) move the patent off Cornice's books in the same window. Note the mechanism is a secured‑lender enforcement/foreclosure‑style transfer rather than an open bankruptcy auction, so the classic public sale docket is absent.

7. Privateering — NOT PRESENT. No evidence that an operating company sponsored Benhov's acquisition or directed assertion of this patent on its behalf. Cornice was not a competing operating company at the relevant time (it was failing), so the privateering template does not fit.

8. Defensive aggregator (anti‑NPE) — NOT PRESENT. The chain terminates at Benhov GmbH, LLC; it does not end at RPX, AST, LOT, Unified Patents, or OIN. There is no evidence this patent has been neutralized.

Verdict

NPE — high confidence.

Three documented, mutually reinforcing signals: (i) a shell/aggregation transfer — Cornice's patent lands in Benhov GmbH, LLC, a no‑products Wilmington, DE holding entity, per reel 019628/0193 (executed 2007‑06‑07, recorded 2007‑08‑01); (ii) cascading/distressed‑lender transfers — three instruments in ~21 months with out‑of‑order recording, reels 018480/0564, 020113/0728, 019628/0193; and (iii) a bankruptcy‑era exit — Cornice failed in 2007 and the patent left with the secured lender (Hercules) rather than through an operating sale. The principal limitation on this verdict is evidentiary: I could not retrieve the assignment correspondents, and I found no suit asserting US 7,571,266; the NPE call rests on the ownership chain and Benhov's aggregation/assertion profile (IPR2017‑00934; Unified Patents parent‑company field = Intellectual Ventures LLC), not on a verified complaint involving this patent.

Verify at: https://assignmentcenter.uspto.gov/ (search patent number 7571266; pull reel 019628/0193 first) and https://patents.google.com/patent/US7571266/en (legal events tab).

I'll research this patent and its cited prior art. Let me run several searches in parallel.

Let me research the remaining cited references.

Prior-Art Analysis — US 7,571,266 B2

1. The target patent (verified against USPTO/Google Patents record)

Core invention: A host (e.g., a microprocessor) with a non-ATA memory interface cannot honor the ATA /IORDY handshake. Instead of extending the bus cycle, the host connects the drive's de-asserted /IORDY to an interrupt input, and on that interrupt simply retries the whole data-transfer operation (e.g., re-issues READ SECTORS). This is viable because modern drives de-assert /IORDY only rarely.

Source: https://patents.google.com/patent/[US7571266B2](/patent/US7571266B2)/en

Analytical caveat (important). The seven references below are the "Patent Citations" listed on the face of US 7,571,266. Being cited does not mean a reference anticipates a claim. Anticipation under 35 U.S.C. § 102 requires a single reference to disclose every limitation of a claim, arranged as claimed. Based on the disclosure I could retrieve, none of these seven references contains the full combination (non-ATA host + /IORDY de-assertion routed to an interrupt input + host-initiated retry). Several are better characterized as § 103 obviousness references for individual building blocks. I state per-reference where § 102 might be argued and where it clearly fails.

2. The seven cited patent references

(1) US 4,845,614 A — Hitachi, Ltd. — "Microprocessor for retrying data transfer"

• Dates: filed 1986-08-12 (JP priority 189201/86, 1986-08-12); published 1989-07-04.
• Description: A microprocessor that automatically retries a bus cycle when a transfer ends abnormally. Uses transfer-response signals (DTACK, BERR, HALT/RMA) to request a retry; counts retries and inhibits retrying past a limit, and inhibits retry for special (I/O) address spaces. An external input signal can initiate retry of a bus cycle.
• § 102 assessment: This is the closest of the group on the retry concept and is the strongest § 102/§ 103 reference against the broad "instruct the peripheral to retry" idea. However it does not disclose: a peripheral that generates a de-asserted /IORDY-type signal; connecting that signal to an interrupt input of the host interface; an ATA-drive/non-ATA-host pairing. So it cannot fully anticipate independent claims 1, 7, 13, 14, 15, or 19 as written. It is a plausible § 103 reference against the retry limitations of claims 1(b), 13, 15, 19.
• Source: https://patents.google.com/patent/[US4845614A](/patent/US4845614A)/en

(2) US 4,989,113 A — Texas Instruments Incorporated — "Data processing device having direct memory access with improved transfer control"

• Dates: filed 1987-12-28 (priority 1987-03-13); published 1991-01-29.
• Description: Microcomputer with an on-chip DMA controller whose start/stop/abort behavior is controlled by a multi-bit start code in a control register; permits unconditional abort, stop-after-read/write, and restart/retry of DMA transfers, with source/destination synchronization via interrupts. Enables flexible abort-and-restart (retry) of transfers.
• § 102 assessment: Discloses transfer abort/restart mechanisms, which touch the "retry" limitation of claims 1(b), 13, 19. It discloses nothing about ATA//IORDY, about an interrupt input carrying a peripheral's ready/wait signal, or about a bus-cycle that cannot be extended. It does not anticipate any claim; at most a § 103 reference for the general retry idea.
• Source: https://patents.google.com/patent/US4989113/en

(3) US 5,490,287 A — Canon Kabushiki Kaisha — "Wireless communication device and printing system using the same"

• Dates: filed 1991-04-04; published 1996-02-06.
• Description: As titled, a wireless communication device and a printing system using it. Note: I could not retrieve the full specification within the search budget, so I am not able to confirm its internal disclosure.
• § 102 assessment: On the face of the title/assignee, this reference appears tangential to the bus-timing/retry subject matter and likely was cited as general background on peripheral-host signaling. I cannot substantiate a § 102 anticipation position for any of claims 1–23 on available evidence. Treat this as unverified.
• Source (record): https://patents.google.com/patent/US7571266B2/en (citations list)

(4) US 5,625,847 A — Kabushiki Kaisha Toshiba — "High-speed ISA bus control system for changing command cycle execution speed by selectively using ISA bus controller and high-speed bus controller"

• Dates: filed 1994-12-26; published 1997-04-29.
• Description: As titled, a bus control system that changes command-cycle execution speed by selecting between a standard ISA bus controller and a high-speed bus controller. Directly concerns bus-cycle timing/duration control. Note: full text not retrieved within budget.
• § 102 assessment: Potentially relevant to the preamble language in claims 1, 7, 14 regarding bus-cycle timing behavior, and to the general notion that a bus cycle's duration is controllable. It does not disclose an /IORDY de-assertion, an interrupt-coupled ready signal, or retry-on-timeout. No § 102 anticipation of any claim is supportable; possible § 103 relevance to the bus-timing context only.
• Source (record): https://patents.google.com/patent/US7571266B2/en

(5) US 5,732,250 A — Intel Corporation — "Multi-function microprocessor wait state mechanism using external control line"

• Dates: filed 1994-09-15; published 1998-03-24.
• Description: A microprocessor with bus control logic driven by a single external pin (RDYRCV) that inserts a variable number of wait states to lengthen the bus cycle, based on the identity of the external component. The control signal is generated by programmable logic (FPGA) that decodes bus addresses and applies a "wait state profile." This is a direct analog to extending bus cycle timing for slow peripherals.
• § 102 assessment: Strong § 103 reference for the bus-cycle-extension concept underlying the preamble of claims 1, 7, 13, 14, 15, 19. But crucially, Intel teaches that the host/FPGA grants the extension (inserts wait states) — the opposite of the invention's point, which is that the host cannot extend timing and instead retries. Also all elements (ATA//IORDY, interrupt-coupled ready signal, retry) are absent from this reference. No § 102 anticipation; meaningful § 103 reference.
• Source: https://patents.google.com/patent/US5732250

(6) US 5,850,555 A — Advanced Micro Devices, Inc. — "System and method for validating interrupts before presentation to a CPU"

• Dates: filed 1995-12-19; published 1998-12-15.
• Description: As titled, validating/qualifying interrupts before they are presented to a CPU. Concerns the interrupt-input pathway. Note: full text not retrieved within budget.
• § 102 assessment: Potentially relevant to the interrupt-input limitations that distinguish the invention's claims — specifically claims 1(b), 7(c), 13, 15, 18, 22 (the "specific signal ... connected to an interrupt input ... through the interrupt input"). Because the reference is about validating interrupts generally, and (per available evidence) does not disclose routing an /IORDY-type ready signal to an interrupt to trigger a retry, it does not anticipate any claim. Possible § 103 use for the "use an interrupt input" limitation only.
• Source (record): https://patents.google.com/patent/US7571266B2/en

(7) US 6,477,596 B2 — Sanyo Electric Co., Ltd. — "Bus controlling method and apparatus for delaying activation of a bus cycle"

• Dates: filed 1996-09-20; published 2002-11-05.
• Description: Bus controller that delays activation of a bus cycle (inserts idle states) based on a device's output-disable-time parameter from the immediately preceding cycle, to avoid data conflicts without unnecessary performance loss. Concerned with bus-cycle timing/delay.
• § 102 assessment: Relevant only to the bus-cycle-timing context (preambles of claims 1, 7, 14 and dependent claims 4/10/17 mentioning "dynamic extension of bus cycle timing"). It does not disclose any peripheral-generated ready/wait signal, interrupt coupling, or retry. No § 102 anticipation.
• Source: https://patents.google.com/patent/[US6477596B2](/patent/US6477596B2)/en

3. Non-patent literature cited (4)

Source: https://patents.google.com/patent/US7571266B2/en

4. Overall § 102 / § 103 conclusion

No single cited reference anticipates any claim of US 7,571,266 under § 102. The claimed combination is:

1. a host incapable of dynamically extending bus cycle timing (non-ATA memory interface);
2. a peripheral (ATA disk drive) that generates a specific signal (/IORDY de-assertion) when it needs an extension; and
3. that signal wired to an interrupt input of the host, causing the host to retry the operation.

The prior art splits these threads:

• Retry-after-error / abort-restart: US 4,845,614 (Hitachi) and US 4,989,113 (TI) — cover element (3)'s "retry" idea but neither couples it to a peripheral's ready//IORDY signal or to an interrupt input.
• Bus-cycle extension / wait states / cycle delay: US 5,732,250 (Intel), US 5,625,847 (Toshiba), US 6,477,596 (Sanyo) — cover bus-timing control, but they grant the extension rather than retry, and none involves /IORDY on an interrupt input.
• Interrupt handling: US 5,850,555 (AMD) — covers interrupt validation, not the peripheral-signal-to-interrupt-to-retry chain.
• Interfacing ATA drives to non-ATA hosts: the Intel PXA27x application note and QuickLogic manual provide the § 103 environment (claims 3/9/16/20) but not the retry mechanism.

Most exposed claims (i.e., where a § 103 combination is most plausible): the broad method/system claims 1, 7, 13, 14 and the bus-cycle-oriented independent claims 15, 19, if the examiner were to combine Hitachi/TI (retry) with Intel '250 (wait-state control) and the Intel PXA27x application note (ATA-on-memory-bus). Least exposed (strongest differentiators): the /IORDY-specific and interrupt-edge-specific dependents 4–6, 10–12, 17–18, 21–23, because the interrupt-input routing of /IORDY and the negative-edge-sensitive configuration are not shown in any cited reference.

Confidence flags: I retrieved and reviewed substantive text for US 4,845,614, US 4,989,113, US 5,732,250, and US 6,477,596. I did not retrieve full text for US 5,490,287, US 5,625,847, or US 5,850,555 within the search budget; my statements about those three rest only on their titles, dates, and assignees from the patent's citation list and should be verified against the full specifications before being relied upon. I have not independently confirmed the exact § 102/§ 103 basis the examiner assigned to each reference (e.g., via the file wrapper / Office actions), so treat the per-claim mapping above as analyst inference, not a record of the examiner's grounds.

I'll verify the prior-art references from the page before building the § 103 analysis.

Let me verify the remaining references, especially the non-patent literature and the closely-related retry/timeout references.

Obviousness Analysis — US 7,571,266 B2

Patent: US 7,571,266 B2, "Peripheral device in a computerized system and method"
Inventor: Lance R. Carlson · Filed/Priority: 2006‑02‑06 · Granted: 2009‑08‑04
Current assignees of record (page): Cornice Inc / Benhov GmbH LLC
Claims analyzed: 1–23

Scope note / honesty flag: The analysis below is built from the prior-art section of the patent page you supplied (7 examiner-cited U.S. patents, 4 examiner-cited non-patent items, and the "Similar Documents" / "Cited By" entries). I searched to confirm the disclosure of the most important references. I could not fully verify the substantive content of the Intel PXA27x VLIO application note, the QuickLogic QuickIDE manual, US 5,490,287, US 4,989,113, or US 5,625,847 within my available steps; where I rely on those, I say so explicitly. I do not claim to have run a complete infringement/validity search.

1. The claimed subject matter, distilled

Independent claim 1 (method) and claim 7 (system) reduce to two required elements:

The disclosed point of novelty is not the retry per se, and not the interrupt per se — it is the combination: (i) routing a timing-extension request (IORDY) to a latching interrupt input on a host that has no IORDY logic, because a non-interrupt GPIO cannot reliably sample a brief transient; and (ii) choosing retry over cycle extension, justified by the specification's premise that modern drives de-assert IORDY rarely (col. describing "the probability of IORDY being de-asserted is generally low").

2. Mapping the cited prior art to elements A–D

3. The obviousness case

3.1 Primary combination — US 6,658,510 + Maxtor ATA/ATAPI‑5 (optionally + Intel PXA27x App. Note)

This is the strongest attack, and it is not among the seven references the examiner cited — US 6,658,510 appears on the page only under "Similar Documents." That is itself a notable prosecution-quality observation.

• US 6,658,510 discloses a microprocessor 108, a peripheral bus 106, a peripheral 104 that "is expected to return an indication … that it is ready," a hung-bus detector 110 that generates a bus-timeout interrupt when the ready indication is late, and a software retry routine 212 invoked from the interrupt handler. That is elements B/C/D with the roles of "host," "ready signal," "interrupt," and "retry" all present in a single reference. (Google Patents; US 6,658,510 PDF)

• Maxtor ATA/ATAPI‑5 supplies the ATA-specific vocabulary the claims recite (IORDY assertion/de-assertion; PIO modes; READ SECTORS), and the Intel PXA27x application note supplies the express motivation to hang an ATA HDD off a non-ATA memory bus.

• The only differences between the combination and claims 1/7/13/14/15 are: (i) the "not ready" signal is the ATA drive's own IORDY output rather than a generic ready line; and (ii) the retry trigger is routed directly to a host interrupt input rather than to a standalone detector that then interrupts.

Why a POSITA would combine. The Intel application note and QuickLogic manual frame "ATA HDD → non‑ATA VLIO/memory interface" as a known, desirable task for portable devices (cell phones, MP3 players, DVRs, PDAs — the patent's own recited field). Once a designer is committed to that architecture and discovers the host has no cycle-extension capability, US 6,658,510 and US 4,845,614 present a known, prepared solution for exactly the class of problem — peripheral slower than the fixed bus cycle — with a known, predictable result (re-issue the operation). KSR Int'l Co. v. Teleflex, Inc., 550 U.S. 398 (2007), makes the substitution of a known technique into a known system, yielding predictable results, a textbook §103 rationale; no explicit teaching, suggestion, or motivation in the references is required.

3.2 Secondary combination — US 4,845,614 + Intel PXA27x App. Note + Maxtor ATA/ATAPI‑5

US 4,845,614 is the examiner-cited reference closest to the claimed remedy. Its abstract states that the microprocessor and peripheral communicate over a bus, and "if an error occurs during the communication, the microprocessor starts the next bus cycle and commands retry of the data communication"; it also counts retries and inhibits retry after a limit (the '266 patent's spec is silent on a retry cap — a further hint that the retry-by-signal concept was old). (EPO counterpart EP 0 256 267)

The Intel PXA27x note (Oct. 2005 — before the 2006‑02‑06 priority) supplies the ATA-on-non-ATA bus motivation and the ATAPI‑5 spec supplies IORDY. Combining them yields element A (peripheral asserts a specific signal requesting more time), B (host without the native timing logic), and C (host re-issues the operation upon that signal).

3.3 Tertiary combination — US 5,850,555 + US 5,732,250 + US 6,658,510

• US 5,850,555 supplies the interrupt-validation/latching teaching that answers any argument that "routing IORDY to an interrupt input" is non-obvious — the '266 specification itself concedes that GPIOs configured as interrupts "almost always latch the occurrence of the interrupt condition" and that non-interrupt GPIOs "typically do not have a latching circuit/function." Note also the specification's own fallbacks — an inverter for a positive-edge-only input, or an external latch with a GPIO reset for a read-only input — are recited as modifications "obvious to one with ordinary skill in the art." A patent that characterizes its own remaining design choices as routine supplies a ready-made obviousness admission.
• US 5,732,250 establishes that a single externally driven control line into a microprocessor is the standard way to let a slower peripheral influence the host bus cycle, and that bus-cycle timing is a design variable ("multi-function … mechanism," programmable wait-state profiles for different components). Multiplying that known flexibility by the known retry remedy is a predictable combination, not an inventive leap.

3.4 Claim-by-claim dispositions (illustrative)

4. The best non-obviousness arguments, and why they are weak

1. "The art taught away — everyone else extended the cycle."
   US 5,732,250 and US 6,477,596 do pursue wait-state/idle-state insertion, and QuickLogic's QuickIDE bridges ATA timing in hardware. But teaching away requires that the art "criticize, discredit, or otherwise discourage" the claimed solution. Retry-on-not-ready was already an accepted alternative in US 4,845,614 and US 6,658,510; two roads to the same destination is the classic KSR situation, not teaching away. Moreover, US 6,477,596 explicitly weighs the cost of always inserting idle states and inserts them "only when it is necessary" — an express preference for avoiding unconditional delay, which supports the '266 rationale.

2. "Claim 19 requires re-responding notwithstanding a successful response."
   The recitation of re-doing a successful transfer reads counter-intuitive, and it is the most useful hook for the patentee. But the reason it succeeds is the specification's own premise — IORDY de-assertions are rare — which makes retry cheap and the risk of repeat loops negligible. A low-probability, bounded-cost fallback is exactly the kind of predictable engineering tradeoff KSR treats as obvious; the specification does not disclose a retry counter or loop guard, so it cannot claim that as the inventive contribution.

3. The "incapable of dynamically extending" negative limitation.
   Negative limitations describing a host's deficiency are, standing alone, entitled to little weight; they are satisfied by every generic memory-interface microprocessor of the era (as the Intel PXA27x note and QuickLogic manual attest). They do not convert a retry mechanism into a patentable advance.

4. Secondary considerations.
   No evidence of unexpected results, commercial success, long-felt-but-unsolved need, or copying is presented on the page. Given the "incapable" host is the pre-existing state of the art and the retry mechanism is directly imported, there is a nexus problem for any secondary-consideration argument. The most probative objective fact — that Texas Instruments filed US 2009/0049209 A1 / US 7,739,440 B2 on 2007‑08‑16 to solve "ATA HDD interface for personal media player … increased data transfer throughput" — is post-filing and therefore cannot be used as §103 art, though it does illustrate how quickly and predictably the field moved once the portable-HDD problem was framed.

5. Conclusion

On the record of this page, claims 1–23 of US 7,571,266 would, in my assessment, be vulnerable to a §103 challenge, with the strength of the challenge depending heavily on references that the examiner apparently did not consider:

• The single most damaging reference, US 6,658,510 ("Software method to retry access to peripherals that can cause bus timeouts during momentary busy periods," Dec. 2, 2003), appears on the page only in the "Similar Documents" list — it discloses the bus, the peripheral-readiness expectation, the interrupt signaling the host, and a software retry routine. Combined with Maxtor ATA/ATAPI‑5 (IORDY / PIO) and the Intel PXA27x VLIO application note (the ATA-HDD-on-non-ATA-host motivation), it renders claims 1/7/13/14/15/19 obvious by the KSR "known technique, predictable result" rationale.
• The examiner's own US 4,845,614 (retry of a bus cycle triggered by an external signal, with retry counting) plus the PXA27x note / ATAPI‑5 supplies an independent, fully-cited path to the same conclusion.
• The dependent claims fall to the ATA/ATAPI‑5 specification (IORDY de-assertion, PIO mode, READ SECTORS) and to routine design choices that the '266 specification itself labels obvious (inverter for edge polarity; external latch for non-interrupt GPIOs).

Caveats I want to state plainly: (a) I have not verified the full text of the Intel PXA27x application note, the QuickLogic QuickIDE manual, US 5,490,287, US 4,989,113, or US 5,625,847, so my mapping of those to specific limitations is provisional; (b) the QuickLogic QuickIDE Bridge User Manual is dated only "2006," which squarely straddles the 2006‑02‑06 priority date — its §102/§103 status requires a documented publication date, and the QuickLogic IDE Host Controller data sheet I located is dated 2008 and is therefore not prior art here; (c) the Intel PXA27x Developer's Manual is dated Jan. 2006, so its own prior-art date needs documentary proof as well; (d) this is a validity analysis of claim scope only and assumes no relevant art outside the page's prior-art section; and (e) nothing here is a legal opinion or a freedom-to-operate/infringement conclusion.