Prior art

To identify the most relevant prior art for US patent 7439623, I will access the USPTO database for the specified patent number and examine its cited references. Prior art citations are critical for evaluating the novelty and non-obviousness of an invention.

Since I cannot directly interact with a live USPTO database in real-time, I will use the authoritative patent text provided earlier in our analysis, which includes a "Prior art keywords" section and a reference to "Japanese Unexamined Patent Publication (Kokai) No. 2000-331991" in the description of the conventional method. This Japanese patent is explicitly presented as a reference for the conventional method that US7439623 seeks to improve upon.

Based on the provided patent text, the most relevant prior art explicitly mentioned is:

• Japanese Unexamined Patent Publication (Kokai) No. 2000-331991
  • Publication/Filing Date: The full patent text states that the "Prior art date" for US7439623B2 is 2003-12-03. While the specific publication or filing date for Japanese Unexamined Patent Publication (Kokai) No. 2000-331991 is not explicitly stated, it is referenced as a conventional method, implying it predates the priority date of US7439623.
  • Brief Description: This patent describes a conventional method for forming a multilevel interconnection structure using copper (Cu) as an interconnect material. It details the formation of a first interconnect buried in an insulating film, followed by layers of SiN, SiO2, and FSG. A via hole is formed through the SiO2 and SiN films to reach the first interconnect, and an interconnect trench is formed in the FSG film to reach the via hole. A barrier film and Cu film are then buried to form a via and a second interconnect. A SiN film is subsequently formed over the structure. This conventional structure is explicitly shown in FIGS. 19B and 19C and its manufacturing process in FIGS. 18A-18C and 19A.
  • Which claim(s) it potentially anticipates under 35 U.S.C. § 102: This prior art describes the conventional problems (void formation due to vacancy movement) that the inventions of US7439623 aim to solve. Therefore, it forms the basis for demonstrating the novelty and non-obviousness of all claims in US7439623 that introduce dummy vias or insulating slits to address these issues. Specifically, any claim in US7439623 that describes an interconnection structure or method without the additional features (dummy vias, insulating slits, etc.) to mitigate void formation would likely be anticipated by this prior art. It directly anticipates the basic structure of a multilevel interconnection using Cu vias and interconnects, as well as the manufacturing steps for forming them, as described in the "BACKGROUND OF THE INVENTION" section of US7439623.