Obviousness

To assess the obviousness of US patent 7439623 under 35 U.S.C. § 103, we must consider whether the claimed invention, at the time of the invention (priority date: 2003-12-03), would have been obvious to a person having ordinary skill in the art (POSA) based on existing prior art. The patent itself identifies key prior art and the problem it aims to solve.

Primary Prior Art Reference:

The background section of US 7439623 explicitly describes a "conventional multilevel interconnection structure" and a "conventional method for forming" it, referencing Japanese Unexamined Patent Publication (Kokai) No. 2000-331991 (JP 2000-331991). This conventional structure, illustrated in FIGS. 19B and 19C of US 7439623, includes:

• A lower interconnect (2) buried in an insulating film (1).
• A SiN film (3), a SiO2 film (4), and an FSG film (5) formed over the insulating film (1) and the lower interconnect (2).
• A via hole (6) through the SiO2 film (4) and SiN film (3) reaching the lower interconnect (2).
• An interconnect trench (7) in the FSG film (5) reaching the via hole (6).
• A barrier film (8) and a Cu film (9) filling the via hole (6) and interconnect trench (7), forming a via (10) and a second (upper) interconnect (11).
• A SiN film (12) formed on the FSG film (5) and the upper interconnect (11).

Crucially, US 7439623 clearly identifies the drawback of this conventional structure: "A large number of vacancies are present in the Cu film 9 deposited by plating. When the multilevel interconnection structure is held at high temperature, these vacancies move along the gradient of stress." Specifically, vacancies flow from the wider second interconnect (11) into the narrower via (10) due to differences in tensile stress, leading to "plastic deformation" and the creation of a "void 13" in the via hole (6), which causes device malfunction.

General Knowledge in the Art:

Prior to December 2003, the problems of electromigration and stress migration in copper interconnects, leading to void formation and reliability issues, were well-known in the semiconductor industry. Techniques for mitigating these issues, such as modifying interconnect layouts, using different barrier materials, or introducing "dummy" structures for various purposes (e.g., improving CMP planarity, managing stress, or improving etching uniformity), were also part of the general knowledge of a POSA. The inclusion of "dummy via" in the "Prior art keywords" of US 7439623 further suggests the general concept of dummy features was recognized.

Obviousness Argument for the "Dummy Via" Concept (First, Third, Fourth, and Fifth Embodiments):

US 7439623 addresses the identified problem of via voiding by introducing one or more "dummy vias" connected to the upper interconnect near the active via. The core idea is that these dummy vias provide alternative "sinks" for vacancies migrating from the upper interconnect, thereby reducing the stress gradient to the active via and suppressing void formation.

A POSA, presented with the conventional structure of JP 2000-331991 and its explicitly stated problem of vacancy-induced via voids, would have a strong motivation to find ways to alleviate stress concentrations and redirect vacancy flow. Knowing that dummy structures can influence material processes and stress, it would have been obvious for a POSA to:

1. Introduce a Dummy Via: A POSA would consider adding a non-functional (dummy) via connected to the upper interconnect (11) and located near the active via (10). This would create an additional site for vacancies to accumulate, dividing the vacancy flow and reducing the number of vacancies reaching the critical active via. This is an intuitive application of creating an "alternative sink" to a known problem of localized accumulation.

2. Optimize Dummy Via Placement and Depth (e.g., First Embodiment): Once the concept of a dummy via is established, a POSA would seek to optimize its effectiveness. The first embodiment of US 7439623 describes the bottom of the dummy via being located in the second insulating film, making it deeper than the active via. The patent claims this creates a steeper stress gradient to the dummy via, making vacancies flow into it preferentially. Given the known mechanism of stress-driven migration, a POSA would be motivated to modify the dummy via's depth to achieve a more favorable stress gradient and enhance its vacancy-capturing ability. Extending an etch for a dummy feature to a lower insulating layer would be a straightforward process modification within the skill of the art.

3. Optimize Dummy Via Dimensions and Shape (e.g., Third and Fourth Embodiments): Similarly, features like a smaller diameter (third embodiment) or a rectangular shape (fourth embodiment) for the dummy via would be obvious design choices for a POSA seeking to optimize the stress profile and vacancy-trapping capacity. If a smaller volume or a specific shape was found to create a steeper or more effective stress trap, a POSA would be motivated to implement these as routine design optimizations. The stated purpose in the patent—to make the stress gradient steeper or to block vacancies more effectively—directly corresponds to known principles of electromigration mitigation.

4. Alternative Dummy Via Locations (e.g., Fifth Embodiment): Providing the dummy via above the upper interconnect (fifth embodiment), rather than below, would also be an obvious alternative. The fundamental principle of creating a vacancy sink connected to the upper interconnect near the active via remains the same, regardless of whether it extends into a lower or upper dielectric layer, depending on design flexibility and manufacturing convenience.

Obviousness Argument for the "Insulating Slit" Concept (Sixth and Seventh Embodiments):

US 7439623 also proposes forming an "insulating slit" within the upper interconnect (11) near the active via (10). The patent explains that this slit reduces tensile stress on the adjacent interconnect portion and acts as a barrier against the movement of atoms or vacancies.

A POSA, aware of the electromigration problem described in JP 2000-331991, would also consider introducing structural barriers to vacancy flow or ways to modify localized stress. Knowing that insulating materials can serve as diffusion barriers and influence mechanical stress in metal lines, it would have been obvious for a POSA to:

1. Introduce an Insulating Slit: A POSA would be motivated to form an insulating slit within the upper interconnect near the via. This would achieve two known benefits:

   • Stress Reduction: The insulating material, with different mechanical properties than copper, could locally reduce the tensile stress within the copper interconnect, thereby reducing the driving force for vacancy migration toward the via.
   • Physical Barrier: The insulating slit would act as a physical impediment, blocking the direct path of vacancy flow within the copper interconnect and preventing them from reaching the via.

2. Optimize Insulating Slit Design (e.g., Sixth and Seventh Embodiments): Once the concept of an insulating slit is adopted, its specific dimensions (e.g., length, such as "greater than or equal to twice and less than or equal to four times as large as the diameter of the via") and placement (e.g., being in contact with or slightly spaced from the via-connected portion) would be obvious optimizations for a POSA. The patent's explanation that a longer slit or a specific placement improves vacancy blocking or stress relief aligns with routine engineering optimization to enhance the desired effect.

Conclusion:

The conventional structure described in JP 2000-331991 clearly establishes the problem of via voiding due to stress-driven vacancy migration. The solutions proposed in US 7439623—introducing dummy vias or insulating slits—are applications of known principles of electromigration and stress migration mitigation. A person having ordinary skill in the art, faced with the problem articulated in JP 2000-331991, would have been motivated to combine the teachings of JP 2000-331991 with general knowledge of dummy structures and stress/electromigration barriers in semiconductor manufacturing to arrive at the claimed inventions. The specific structural and dimensional features claimed are primarily optimizations of these fundamental concepts, which a POSA would routinely explore to improve interconnect reliability. Therefore, the claimed inventions in US 7439623 would likely have been obvious under 35 U.S.C. § 103 when considered in light of JP 2000-331991 and the general knowledge of the art.