US 7272805

I'll verify this against live sources before summarizing.

Now let me check for any CAFC litigation or 2026 docket activity involving this patent.

US Patent 7,272,805 — Verification Summary

Sources retrieved: Google Patents (https://patents.google.com/patent/[US7272805](/patent/US7272805)/en), Justia Patents (https://patents.justia.com/patent/7272805), USPTO publication PDF of US2006/0112356A1 (https://patentimages.storage.googleapis.com/d7/1f/c9/457dc5bc38fe6b/US20060112356A1.pdf), Patent Leaderboard inventor records. Docket searches for Federal Circuit / CAFC 2026 activity returned no results (see Litigation note below).

Bibliographic data (as recorded in the fetched authoritative text)

Note on dates: your prompt gives "Current Date: April 26, 2026," while the authoritative page was fetched with a timestamp of 2026-09-27. I'm flagging the discrepancy rather than silently resolving it; all status information below is stated as of the source text, not adjudicated as current legal fact.

Abstract (verbatim)

"System and method for converting a flat netlist into a hierarchical netlist are disclosed. The method includes receiving the flat netlist, traversing the flat netlist in a bottom-up fashion, and identifying isomorphic subcircuits in the flat netlist. The method further includes creating a set of cross-coupling capacitor collections for storing information of cross-coupling capacitors, creating a set of net collections for storing information of isomorphic subcircuits, traversing each hierarchical level of the hierarchical netlist in a top-down fashion, and generating the hierarchical netlist using the set of net collections and the set of cross-coupling capacitor collections."

Plain-language overview of the three independent claims

(Claims 1, 17, and 33 are the only independents; claims 2–16, 18–32, and 34–48 depend from them.)

Claim 1 — Method. A computer-implemented method with six recited steps: (1) receive a flat netlist; (2) walk it bottom-up and identify isomorphic (electrically/structurally equivalent) subcircuits; (3) build a set of cross-coupling capacitor collections holding data about cross-coupling (wire-to-wire) capacitors; (4) build a set of net collections holding data about the isomorphic subcircuits; (5) walk each level of the hierarchical netlist top-down and generate the hierarchical netlist using those two collections; and (6) store the resulting hierarchical netlist in a memory device. In substance: turn a physically-accurate but huge flattened parasitic netlist into a compact, simulation-friendly folded hierarchy.

Claim 17 — System. The apparatus counterpart. It requires at least one processing unit, a user interface (for one of: entering a netlist representation, viewing circuit representations on a display, or observing simulation results), a memory storing the flat and hierarchical netlists, plus means-plus-function elements mirroring claim 1's steps — means for receiving, means for bottom-up traversing/identifying isomorphic subcircuits, means for creating cross-coupling capacitor collections, means for creating net collections, means for top-down generating the hierarchical netlist, and means for storing it in memory.

Claim 33 — Computer program product. The Beauregard-style counterpart: a medium storing computer programs, comprising a netlist conversion module usable with a processing unit, user interface, and memory, containing instructions for the same six-step sequence recited in claim 1 (receive → bottom-up traverse/identify isomorphic subcircuits → create cross-coupling capacitor collections → create net collections → top-down generate the hierarchical netlist → store in memory).

Representative dependent-claim subject matter (for scope context)

• Cross-CC collection contents (claims 2, 18, 34): the capacitor, call paths from the highest level down to the lowest-level subcircuit it couples to, and its nodes.
• Net collection contents (claims 4, 20, 36): anchor node, upper call paths from the top level to the anchor node, an RC subcircuit containing back-annotated parasitic elements, and lower call paths from the anchor node to connected parasitic elements.
• Net-collection creation loop (claims 5, 21, 37): per-parasitic-net steps (a)–(f), including identifying an anchor subcircuit/anchor node, building the RC subcircuit, "optimizing duplicate anchor nodes," and updating the collection.
• Isomorphism test (claims 8, 24, 40): same set of input signals; same internal topologies, states, and external loads; and outputs within a predetermined tolerance in response to the same inputs.
• Cross-coupling capacitance handling (claims 9, 25, 41): summing expected vs. arrived Cross-CC per node and averaging.
• Top-down generation machinery (claims 10, 26, 42 and dependents): forming an NCset array, splitting a subcircuit when more than one upper call path exists, stitching it into the hierarchical netlist, associating it with the next level, and level-by-level iteration (including the swap/increment of the next-level subcircuit set).

Litigation / CAFC check

• Federal Circuit (CAFC) 2026 dockets: targeted searches for "7272805" / "7,272,805" in connection with the Court of Appeals for the Federal Circuit returned no hits. I found no appeal, IPR appeal, or other CAFC proceeding involving this patent.
• District court: searches surfaced only Cadence's unrelated 2025–2026 litigation (e.g., Cadence Design Systems, Inc. v. Yunjing Intelligent Innovation (Shenzhen) Co., Ltd., N.D. Cal. 3:25-cv-00317, a DMCA/software-license case; and Cadence/Synopsys v. Bell Semiconductor declaratory-judgment actions over the '259, '807, '760, '803, '626, and '989 patents). No case asserting or challenging US 7,272,805 was found.
• Caveat: absence of results is not proof of absence. Docket databases are not fully indexed in general web search, and this patent expired for non-payment of maintenance fees in 2019, which makes assertion unlikely. I did not independently access PACER, the CAFC docket system, or USPTO PatentCenter/Assignment records to confirm.

Prior-art citations of record (per the fetched text)

• US 5,446,676 A — Epic Design Technology (1995)
• US 5,553,008 A — Epic Design Technology (1996)
• US 6,665,845 B1 — Sun Microsystems (2003)

Plus non-patent literature including the Celestry BSIM Pro+ manuals, Feldman et al. (1995), Kerns et al. (1996), Pillage et al. (1990), and U.S. Appl. Nos. 10/724,277 and 10/993,687.

Uncertainty flags

1. Status currency: The "Expired – Fee Related / lapse effective 2019-09-18" entry is as listed on the fetched page; I have not confirmed it against USPTO PatentCenter today.
2. Assignee currency: Cadence Design Systems, Inc. is listed as both original and current assignee; Google Patents explicitly disclaims accuracy of assignee/reassignment data. No chain-of-title documents were reviewed.
3. Date conflict: the operating date given in your prompt (2026-04-26) differs from the source fetch timestamp (2026-09-27); this does not change any bibliographic fact above, but it affects any statement about present-day status.
4. No CAFC activity should be read as "none found in web-indexed sources," not as a certified negative.

I'll search for litigation involving US patent 7272805 across patent litigation databases.

Let me search more targeted litigation databases for this specific patent.

Let me do a few more targeted checks before concluding.

Litigation Search Result: US Patent 7,272,805

Conclusion: No litigation is known to involve US Patent 7,272,805.

I was unable to identify any district court action, Federal Circuit appeal, ITC Section 337 investigation, or PTAB proceeding (IPR/PGR/CBM) naming US 7,272,805 as an asserted, challenged, or otherwise-in-suit patent. The patent appears to be a defensive/portfolio asset of its owner that has not been litigated.

Patent identification (for the record)

What the searches did and did not show

• Litigation databases / general web: Searches for "7272805," "7,272,805," and the patent title returned only the patent's own Google Patents page, inventor/assignee portfolio pages (e.g., PatentLeaderboard listings for Boris Krichevskiy and Peter Frey), and unrelated matters.
• "Cited By" / "Similar Documents" (Google Patents): US 7,272,805 appears only as a citation or related document in later patents (e.g., Cadence's US 7,434,183; LSI's US 7,676,773; Raytheon's US 9,830,414; etc.). Being cited by later patents is not evidence of litigation.
• Cadence's own SEC filings: Cadence 10-K reports describe EDA-industry patent disputes (e.g., the Bell Semiconductor campaign beginning April 27, 2022, and the Mentor/Quickturn matters), but none identify US 7,272,805 as asserted.

Important caution — do not confuse with similarly-numbered "280" patents

My searches surfaced several different patents whose numbers or shorthand include "280." These are not US 7,272,805 and must not be attributed to it:

• US 6,895,280 — Boston Scientific (spinal cord stimulation) '280 patent, litigated in Boston Scientific v. Nevro (D. Del., C.A. No. 16-1163), incl. an IPR.
• US 9,272,280 — Hemosonics (hemostasis), subject of IPR2017-00852.
• The "Watson/Actavis '280 Patent" in the New Jersey ANDA complaint is yet another unrelated patent.

Confidence and limitations

• High confidence that no litigation is disclosed in the accessible public sources I searched.
• Caveat: I could not run an exhaustive, database-native query (e.g., a direct PACER docket lookup, Unified Patents litigation portal case-list query, or Docket Alarm full-text search) because my access was limited to open web search, and those databases are not fully indexed by general search engines. It remains possible that an obscure or very recent case exists, or that the patent was asserted in a non-US forum (e.g., a counterpart foreign patent), which I did not locate. I found no such case, so I report none.

If you need a definitive negative, the appropriate next step is a native query of the Unified Patents litigation portal, Docket Alarm, LexMachina, or PACER for the exact string "7,272,805" (and its reissue/continuation family), rather than relying on open web search alone.

I'll verify the structured data against what's publicly findable before writing anything up.

The initial searches returned only unrelated hits (a Japanese patent also numbered 7272805, a Brazilian corporate registry number, and Netlist/Samsung matters on different patents). Let me run a few narrower checks before concluding.

No PTAB hits so far — only false positives on the bare digits (a Kyocera Japanese patent JP7272805, a Brazilian company registration number, a BioSample accession). Two more checks to rule out a litigation-driven challenge and a reexam.

Proceedings overview

Total AIA trial proceedings on file for US 7,272,805: zero. The structured PTAB block (USPTO Open Data Portal) returns no IPR, PGR, or CBM for this patent, and four targeted web searches surfaced no proceeding that the ODP has not yet indexed. There is therefore no breakdown by status to report — no proceedings are active, none produced invalidated claims, none produced sustained claims, none settled, and none were denied institution.

The bottom-line defensive posture is unusual and, frankly, better than any PTAB outcome: this is a Cadence Design Systems portfolio patent that has never been asserted in an AIA trial and, per the legal-events timeline, lapsed in 2019 for failure to pay maintenance fees. A demand letter citing US 7,272,805 is not a case you need to invalidate — it is a case you need to date-stamp.

No proceedings to itemize

I ran the format you asked for and it produces an empty list. For the record, the false positives I had to clear:

• JP 7272805 B2 — Kyocera, "水晶素子および水晶デバイス" (quartz element/device), JP App. 2019-12294. Coincidental number collision with the Japanese register, not the US patent.
• Brazilian corporate registration "7272805" (JUCIS-RS ata, JUCEC-CE decisory acts) and a NCB BioSample accession SAMN07272805 — bare-number collisions, irrelevant.
• Netlist, Inc. v. Samsung / Micron results — these concern Netlist's memory-module patents (e.g., IPR2022-00615, IPR2022-01427/01428, IPR2023-00882/00883) and Samsung's '918/'054/'366 challenges. Different patent owner, different patents, no connection to the '805.

Caveat on method: I was cut off before I could pull the PTAB E2E / PTAB Decisions docket directly, so my negative finding rests on (a) the ODP structured block you supplied as canonical and (b) external searches. If you need a belt-and-suspenders clearance before filing, run the number through PTAB E2E and the PTAB Decisions "Patent Number" filter, and re-check CourtListener for the patent number as a party-search string.

What the '805 actually is (grounding for the strategy below)

The claim set is a three-track (method / system / CRM) recitation of: receiving a flat netlist → bottom-up identification of isomorphic subcircuits → building cross-coupling-capacitor collections and net collections → top-down traversal to regenerate the hierarchy. Claim 5 and its dependents (6–9) add the anchor-subcircuit/anchor-node machinery; claims 10–16 add the NCset splitting/stitching steps. All 48 claims are UNTESTED — not "sustained," simply never challenged.

One data conflict you should resolve before relying on the expiration date. The Google Patents header reads "Expired - Fee Related, expires 2025-10-09," but the legal-events timeline in the same record says: 2019-10-21 LAPS — PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.) and 2019-11-12 FP — Expired due to failure to pay maintenance fee, effective date 20190918. The 2019-09-18 date is the 11.5-year maintenance-fee deadline (grant 2007-09-18 + 11.5 years, matching the earlier 2011-03-18 and 2015-03-18 fee payments). The 2025-10-09 figure looks like the projected adjusted statutory expiration (20 years from 2004-11-19 = 2024-11-19, plus roughly 325 days of PTA). Those two cannot both be operative. Confirm in USPTO PatentCenter whether the patent was ever reinstated under 37 C.F.R. § 1.378 — the record shows no reinstatement event, so the overwhelming likelihood is expiration on 2019-09-18, but this is the single fact worth verifying first because it drives everything else.

Strategic summary

Which claims are canceled vs. sustained vs. untested. None canceled, none sustained. All 48 claims stand exactly as granted, but the patent is (apparently) expired, which converts the question from "are the claims valid?" to "was there ever an enforceable right?" For a defendant today, the practical consequence is that § 282 invalidity defenses are largely beside the point: 35 U.S.C. § 286 caps damages at six years before the complaint, so a suit filed now reaches back only to roughly 2020 — entirely after the 2019 lapse. Any theory of recovery would have to rest on pre-lapse conduct that is now outside the lookback window. That is a Rule 12 / summary-judgment posture, not a PTAB posture.

Estoppel landscape. Because no IPR or PGR was ever filed, § 315(e)(2) estoppel is a non-issue — no petitioner, no privies, no barred grounds. A defendant retains the entire universe of § 102/§ 103 art, including the two Epic Design Technology references the examiner cited (US 5,446,676; US 5,553,008) and the Sun Microsystems reference (US 6,665,845) — though this is cold comfort given the expiration. Note also that the Board does institute on expired patents in appropriate cases (applying Phillips claim construction), so an IPR is not categorically unavailable on an expired patent; but there is little reason to spend IPR fees invalidating a patent whose damages tail is already cut off.

Pattern signals. No repeat-petitioner pattern — there is no petitioner at all. No PTAB appeal history, no Federal Circuit appeal of this patent, no defensive aggregator (Unified Patents or similar) in the chain. The ownership story is the opposite of a troll: Cadence is a large-cap EDA vendor that uses patents like the '805 defensively, and this one appears never to have been asserted. That is consistent with the maintenance-fee lapse: sophisticated owners let portfolio patents go when they are not producing licensing revenue.

Recommended next steps

1. If you received a demand letter citing US 7,272,805 — do not assume you need an IPR. Ask the sender for a claim chart and a priority date, then verify the expiration status in PatentCenter. If the patent lapsed 2019-09-18 and was not reinstated, the honest answer to the demand is a short letter: the patent is expired, § 286 limits any recovery to post-2020 activity, and there is nothing to license. Document the lapse date from PatentCenter, not from Google Patents, given the 2025-10-09 discrepancy above.
2. If the sender instead points to a family member or continuation — the '805 itself has no listed continuations, but its siblings (Ser. No. 10/993,687 "Electrical Isomorphism"; Ser. No. 10/724,277 → US 7,181,383) are separate rights with separate expiration clocks. Get the specific patent number and re-run this analysis; do not let the '805's lapse stand in for a live sibling.
3. If you nevertheless want an AIA-trial ruling (e.g., to secure a written invalidity judgment for indemnity or customer-defense purposes) — there is no § 315(b) one-year bar running, since there is no litigation service of a complaint on you that I could find, and no earlier petitioner whose estoppel could constrain you. But weigh the cost against Step 1: invalidity of an expired, unasserted patent rarely changes anyone's settlement posture.
4. For completeness before acting — confirm the negative with the primary sources I could not reach: PTAB E2E docket search by patent number, and the PTAB Decisions "Patent Number" field, both at USPTO. I found no proceeding in the ODP block or in web search, but an affirmative clearance from the Office's own docket is the right foundation for a filing position.

I could not verify any of the following, and I am not asserting them: that the patent was never asserted in district court (my litigation searches returned Bell Semiconductor v. Cadence/Synopsys and older Cadence v. Avant! copyright matters, none involving the '805, but I did not run a complete docket sweep); that no ex parte or inter partes reexamination exists (none appeared on the Google Patents "Also published as"/family record, but reexaminations do not always surface there); and that the maintenance-fee lapse was not cured by reinstatement. Treat the lapse as highly probable and the "no PTAB activity" finding as solid on the evidence available.

I'll verify the assignment record and check for any litigation or downstream transfers before writing up.

Let me confirm whether there is any litigation on this patent and try to pin down the correspondent of record on the assignment cover sheet.

Ownership Reconstruction — US 7,272,805 B2

Patent: System and method for converting a flat netlist into a hierarchical netlist
Application: US 10/993,686 · filed 2004-11-19 · granted 2007-09-18
Current status: Expired — Fee Related (lapsed for non-payment, effective 2019-09-18)
Records reviewed: USPTO Assignment Center / Assignments on the Web (assignment.uspto.gov), Google Patents legal events (authoritative text supplied), related-file records, litigation search.

Inventors

Unusual-pattern check: No anomalous departure signal. All three signed the assignment 2004-10-22 to 2004-10-27 — i.e. before the 2004-11-19 filing date — which is the normal pre-filing employee-assignment practice, not a post-filing exit. I found no evidence of inventors leaving Cadence within 12 months of filing, and I could not confirm or deny later departures with high confidence from public records. No fire-sale precursor here.

Related-file tell: Serial 10/993,687 ("Electrical Isomorphism," now US 7,373,289), filed the same day as this application and expressly incorporated by reference, was assigned to Cadence on the same recording date, same reel series (016019/0494) by McGaughy, Au and Yang. This is a batch recordation of employee invention assignments, not an arm's-length transfer.

Original assignee

Cadence Design Systems, Inc. (Delaware corporation; principal place of business San Jose, California; the assignment records the assignee's address state as CALIFORNIA).

• Line of business: Electronic Design Automation software — schematic capture, simulation (Spectre/SPICE-family), place-and-route (Innovus/Virtuoso), physical verification (Pegasus/PVS). Publicly traded (Nasdaq: CDNS).
• Product embodying the claims: Yes. The patent is a netlist-conversion front-end to Cadence's hierarchical back-annotated simulation technology, whose companion patents — US 7,181,383 (Ser. No. 10/724,277) and US 7,373,289 (Ser. No. 10/993,687) — are incorporated by reference into this specification. The claimed invention (claims 1, 5, 10, 13) is a simulation-preparation tool feature, i.e. shipping EDA software, not a standalone article of commerce.
• Current status: Operating. No bankruptcy, no dissolution, no IP-divestiture programme touching this patent. Cadence remains the record owner.
• Assertion history of the patent itself: None found. Cadence's litigation posture in this space is as a defendant-side actor — it is a co-plaintiff in a declaratory-judgment action against patent monetization entity Bell Semiconductor, LLC (a Hilco IP Merchant Capital company) concerning other patents, D. Del. C.A. No. 1:22-cv-01512, and a copyright/DMCA plaintiff against Yunjing Intelligent Innovation (N.D. Cal. 3:25-cv-00317). US 7,272,805 is not a patent-in-suit in either matter.

Assignment timeline

One recorded conveyance exists for this patent. There is no post-issuance chain.

• 2004-10-22 → 2004-10-27 (executed; per the recorded signing date range) / recorded 2004-11-19 — Reel 016019 / Frame 0535
  • Conveyance: Assignment (of assignors' interest)
  • Assignor: Bruce W. McGaughy; Peter Frey; Boris Krichevskiy (individually)
  • Assignee: Cadence Design Systems, Inc. (CALIFORNIA)
  • Correspondent: Not recoverable from the sources I was able to consult. The Google Patents legal-event abstract and the Assignments-on-the-Web index entry both expose the reel/frame, the conveyancing parties and the signing dates, but not the cover-sheet correspondent block. I am not going to guess it. Note the contrast with the sibling application 10/993,687 (reel 016019/0494), prosecuted through correspondence at Morrison & Foerster LLP, 755 Page Mill Rd, Palo Alto, CA 94304-1018 (per US 2005/0143966 A1); the Cadence assignment recordings in this batch appear to have been handled by Cadence's own panel, not by a recurring NPE-side filing attorney. That is an inference from adjacency, not a record citation — treat as unconfirmed.
  • Context: Employment/obligation assignment — inventors conveying their pre-filing rights to their employer under the standard Cadence invention-assignment practice. Not an acquisition, securitization, or asserter transfer.

No other assignments are recorded. Assignment Center / AOTW shows no Change of Name, Merger, Security Agreement, License, Release, Correction, or further Assignment for US 7,272,805 through the search date. The complete chain of title is inventor → Cadence, and it stays there.

Termination evidence (ownership-relevant, not a transfer):

• 2011-03-18 — 4th-year maintenance fee paid
• 2015-03-18 — 8th-year maintenance fee paid
• 2019-05-06 — maintenance fee reminder mailed (large entity)
• 2019-10-21 — Lapse for failure to pay maintenance fees; patent expired under 37 CFR 1.362, effective 2019-09-18

A patent that a monetizer would have purchased on the way to assertion instead lapsed unsold. Cadence paid two maintenance fees post-issuance and declined the third — consistent with ordinary portfolio pruning of a 2004-vintage simulation utility, not with a value-extraction or divestiture event.

Timeline diagram

timeline
    title Ownership of US 7272805
    2004 : Inventors assign rights to Cadence
         : Application filed 19 Nov 2004
    2007 : Patent granted 18 Sep 2007
    2011 : Fourth year maintenance fee paid
    2015 : Eighth year maintenance fee paid
    2019 : Maintenance fee default 18 Sep 2019
         : Patent lapses and expires

NPE / troll-pattern signals

Verdict

Insufficient data — only the original assignment is recorded.

The complete chain of title for US 7,272,805 consists of a single instrument: the inventors' pre-filing employment assignment to Cadence Design Systems, Inc., executed 2004-10-22 to 2004-10-27 and recorded 2004-11-19 at reel 016019/0535. There is no subsequent assignment, name change, security interest or license on record, and the patent expired for non-payment of maintenance fees effective 2019-09-18, still owned by Cadence. With one recorded link, zero assertion activity and a lapse rather than a sale, no NPE or troll pattern is present or supportable; the correct classification under the framework is the no-chain case, not "operating-company assertion," because no competitor suit on this patent exists.

Verify at the USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/ (patent-number query 7272805), and the mirrored index at https://assignment.uspto.gov/patent/index.html. Source of the reel/frame and legal-event data above: https://patents.google.com/patent/US7272805/en

Caveats and open items (stated rather than inferred):

• The correspondent of record on reel 016019/0535 is not verifiable from the sources I could reach. I could not open the assignment cover-sheet PDF. Anyone needing the correspondent for a repeat-player cross-match should pull the document image from Assignment Center directly.
• My litigation search surfaced Cadence matters involving other patents (Bell Semiconductor DJ action; Yunjing/Narwal DMCA case) but no case naming US 7,272,805. I did not obtain an exhaustive PACER/Docket Alarm docket for this specific patent number, so I state this as "none found," not "none exists."
• The companion application Ser. No. 10/993,687 issued as US 7,373,289 and was assigned on the same date/reel series (016019/0494). If a broader portfolio analysis is wanted, that family — plus US 7,181,383, US 7,024,652 and US 8,428,928 — should be run through the same ownership check; they share the McGaughy inventor overlap and the same Cadence retention pattern.

I'll research this patent and its cited prior art. Let me start by verifying the patent and its citations.

Let me verify the related applications and non-patent references cited in the patent.

Prior-Art Analysis — US 7,272,805 B2

1. Identification of the Patent (verified record)

Note on source: I retrieved the patent record via its Google Patents / Justia mirrors, which reproduce the USPTO front-page data. A direct USPTO PatentCenter listing was not returned in the search, so the bibliographic and citation data below should be read as the Google Patents–hosted USPTO record. No "similar number" results are included; everything below is tied to 7,272,805.

The claims to be tested. Claim 1 (independent method claim) requires: (a) receiving a flat netlist; (b) traversing it bottom-up and identifying isomorphic subcircuits; (c) creating a set of cross-coupling capacitor collections; (d) creating a set of net collections; (e) traversing each hierarchical level top-down and generating the hierarchical netlist using those two collections; and (f) storing the hierarchical netlist in memory. Claims 4, 5, 8, 9, 10–16 add the net-collection data structure, the anchor-subcircuit/anchor-node construction, the "substantially the same isomorphic behaviors" test, the cross-coupling-capacitance averaging, and the NCset split/stitch steps. Claims 17–32 and 33–48 are the system (means-plus-function) and computer-program-product counterparts.

2. Patent References Cited on the Face of 7,272,805

The patent lists three U.S. patent citations. All three predate the 2004-11-19 filing/priority date and are therefore available as prior art under pre-AIA 35 U.S.C. § 102(a)/(b).

2.1 US 5,446,676 A

• Full citation: U.S. Patent No. 5,446,676, "Transistor-level timing and power simulator and power analyzer," inventors Xiaoli Huang and William H. Zhang, assignee EPIC Design Technology Inc. (Santa Clara, CA). Application No. 08/040,531, filed 1993-03-29; issued 1995-08-29.
• Brief description: A transistor-level simulator/analyzer for digital MOS circuits using piece-wise-linear transistor modeling, dynamic/static construction of channel-connected components (CCCs), event-driven simulation, and current measurement for power supplies, grounds and individual elements. It operates on a SPICE-style netlist file and contemplates "subcircuit specifications (i.e., collections of elements)."
• Potential § 102 relevance to 7,272,805: Weak. It discloses netlist handling and the grouping of elements into subcircuits/CCCs, but it does not disclose converting a flat netlist into a hierarchical netlist, identifying isomorphic subcircuits, net collections, or cross-coupling-capacitor collections. It cannot anticipate claim 1 or any dependent claim. At most it is background/general-art evidence that netlists and subcircuit groupings were known, i.e., a possible § 103 reference for the generic "receiving a flat netlist" preamble element, not a § 102 anticipation.
• Claims it could arguably touch: Claim 1 (only the "receiving the flat netlist" element, and even that only generically).

2.2 US 5,553,008 A

• Full citation: U.S. Patent No. 5,553,008, "Transistor-level timing and simulator and power analyzer," assignee EPIC Design Technology Inc. Filed 1993-03-29 (same priority as the '676 patent — a continuation/related filing); issued 1996-09-03.
• Brief description: Substantively the same disclosure as the '676 patent: a transistor-level timing/power simulator operating on SPICE netlists, with technology files, event scheduling, CCC evaluation, and current/time output. Claim 13 of this reference expressly notes that "said netlist of a circuit to be simulated also identifies capacitors and resistors," and the specification discusses subcircuit specifications and subcircuit pin ordering.
• Potential § 102 relevance to 7,272,805: Weak, and essentially duplicative of § 2.1. The reference establishes that netlists identifying resistors, capacitors and subcircuits were known. It contains no teaching of bottom-up isomorphism detection, hierarchical netlist generation, net collections, or cross-coupling-capacitor collections. No claim of 7,272,805 is anticipated.
• Claims it could arguably touch: Claim 1 (preamble/netlist-and-subcircuit context only).

2.3 US 6,665,845 B1

• Full citation: U.S. Patent No. 6,665,845 B1, "System and method for topology based noise estimation of submicron integrated circuit designs," inventors Aingaran, Hoerold, Haritsa and Wang, assignee Sun Microsystems, Inc. Application No. 09/812,406, filed 2001-03-19 (Google Patents lists a prior-art/priority date of 2000-02-25); issued 2003-12-16.
• Brief description: A crosstalk/noise-analysis tool that models coupling between aggressor and victim wires. It uses a two-pole coupling model based on coupling capacitances and ground capacitances lumped on victim-line RC segments (see its FIG. 3), reduces the extracted resistance/capacitance of a signal line prior to computing coupled noise (its FIG. 9 vs. FIG. 10), and explicitly applies the model to a hierarchical netlist (its FIG. 7, "two-pole noise model applied to a hierarchical netlist") with "hierarchical analysis" for speed.
• Potential § 102 relevance to 7,272,805: This is the most pertinent of the three patent citations, because it is the only one that touches both (i) cross-coupling/coupling capacitance and (ii) hierarchical netlist handling. It could be argued to bear on the cross-coupling-capacitor aspects of claims 2, 3, 18, 19, 34, 35 (identifying cross-coupling capacitors and recording their nodes) and on the RC-reduction aspect of claim 6. However, it does not disclose storing cross-coupling capacitors in dedicated collections keyed to call paths from the highest level to a lowest-level subcircuit (the specific structure of claims 2/3/18/19/34/35), nor converting a flat netlist into a hierarchical one, nor net collections isomorphically grouped bottom-up. It therefore does not, standing alone, anticipate claim 1 or its dependents; it is better characterized as a § 103 reference on the coupling-capacitance subject matter.
• Claims it could arguably touch: Claims 2–3, 18–19, 34–35 (cross-coupling capacitor identification and node recording) and claim 6 (RC reduction) by way of obviousness; not an anticipation of claim 1.

2.4 On the "Cited By" and "Families Citing" Lists (excluded)

The record also shows a "Cited By (9/15)" list (e.g., US 2006/0161413, US 7,434,183, US 7,676,773, US 8,414,285, US 8,819,086, US 9,367,659, US 9,830,414, US 10,515,174) and a "Families Citing this family" list. These are forward citations — later documents that cite 7,272,805 — and are not prior art to it. They are noted here only to prevent them being mistaken for § 102 art.

3. Non-Patent References Cited on the Face of 7,272,805

The patent lists eight non-patent citations. All predate 2004-11-19.

3.1 Model-order / RC-reduction literature (most relevant to the RC-subcircuit claims)

(a) Pillage, L.T. et al. (Apr. 1990). "Asymptotic Waveform Evaluation for Timing Analysis," IEEE Transactions on CAD, 9(4):352–366.

• Brief description: The foundational asymptotic waveform evaluation (AWE) paper — moment-matching/model-order reduction of linear(ized) RC interconnect networks for timing analysis.
• Relevance: Bears on claim 6 (forming an RC subcircuit and "optimizing the RC subcircuit … creating a corresponding electrically substantially equivalent RC subcircuit having fewer resistor or capacitor elements"), i.e., RC reduction. It does not address hierarchical netlist conversion, isomorphism, or net collections; it is a § 103 reference, not an anticipation of claim 1.

(b) Kerns, K. et al. (1996). "Stable and Efficient Reduction of Large Multiport RC Networks by Pole Analysis via Congruence Transformations," IEEE/ACM DAC, pp. 280–285.

• Brief description: Multi-port RC-network reduction using pole analysis / congruence transformations — a model-order-reduction technique for large RC networks, including multiport (hence coupling) networks.
• Relevance: Same as (a): supporting art for claim 6's RC-equivalent reduction, and marginally for multi-terminal coupling network handling. Not anticipatory of any claim.

(c) Feldman, P. et al. (May 1995). "Efficient Linear Circuit Analysis by Padé Approximation via the Lanczos Process," IEEE Transactions on CAD, 14(5):639–649.

• Brief description: Lanczos-based Padé approximation (PVL-style model-order reduction) for efficient linear circuit/interconnect analysis.
• Relevance: Again supports the RC-reduction concept of claim 6. Background/§ 103 only; no hierarchical-conversion teaching.

3.2 Device-modeling and SPICE background literature

(d) Celestry Design Technologies, Inc. (2001). Celestry BSIM Pro+™ Basic Operations, User Manual, Version 2001.3, Table of Contents, pp. iii–xiii.
(e) Celestry Design Technologies, Inc. (2001). Celestry BSIM Pro+™ Device Modeling Guide, User Manual, Version 2001.3, Table of Contents, pp. iii–xii.

• Brief description: User manuals for a commercial MOSFET (BSIM-family) device-modeling/extraction tool.
• Relevance: Background evidence that transistor-level device models and parameterized primitive elements were well known — relevant only to the general context (simulation of transistor-level circuits). No bearing on claims 1–48 as anticipation.

(f) Van der Spiegel, J. (1995). "SPICE — A Brief Overview," University of Pennsylvania (URL cited in the patent record).

• Brief description: Tutorial overview of the SPICE circuit simulator.
• Relevance: Background evidence that SPICE-style flat netlists were standard input. Relevant, at most, to the "receiving the flat netlist" preamble of claim 1. Not anticipatory.

3.3 Co-pending / commonly owned applications (subject to a special caveat)

(g) U.S. Appl. No. 10/724,277, filed Nov. 26, 2003, by McGaughy et al. ("System and Method for Simulating a Circuit Having Hierarchical Structure") — granted as US 7,181,383 B1 on 2007-02-20.

• Brief description: A hierarchical circuit simulator using a static database (topology), a dynamic database, and processes of static/dynamic isomorphic partitioning — including identifying circuit components having "substantially the same waveforms at the input ports … substantially the same loads at the output port … and substantially the same states (signal conditions)."
• Relevance: Conceptually the closest document to the isomorphic-subcircuit idea of claim 1 and to the "substantially the same isomorphic behaviors" definition in claim 8. Caveat: this application is expressly incorporated by reference into 7,272,805 and is commonly owned by Cadence. An incorporated-by-reference document is treated as part of the host disclosure rather than as independent prior art, and commonly owned subject matter raises pre-AIA § 103(c) disqualification issues for obviousness. It is therefore better characterized as related/complementary disclosure than as § 102 prior art that anticipates the claims.

(h) U.S. Appl. No. 10/993,687, filed Nov. 19, 2004, by McGaughy et al. ("Electrical Isomorphism").

• Brief description: The companion application filed the same day as the '686 application, directed to electrical isomorphism (the substantive basis for the "substantially the same isomorphic behaviors" test of claim 8).
• Relevance: Same caveat as (g): it is co-owned, filed the same day, and expressly incorporated by reference, so it functions as part of the disclosure rather than as prior art. Note that its 2004-11-19 filing date is not earlier than 7,272,805's date, so it is not prior art on timing grounds either.

4. Bottom-Line Assessment

Most relevant prior art overall: US 6,665,845 B1 (cross-coupling/coupling capacitance + hierarchical-netlist noise analysis) is the single most relevant patent citation. Among non-patent items, Pillage 1990 / Kerns 1996 / Feldman 1995 are the most relevant (they underpin the RC-reduction feature of claim 6).

No cited reference anticipates claim 1. Anticipation under § 102 requires that a single reference disclose every element of the claim. No reference of record discloses the combination of: receiving a flat netlist → bottom-up traversal with isomorphic-subcircuit identification → creation of cross-coupling-capacitor collections → creation of net collections → top-down per-level generation of a hierarchical netlist from those collections. The cited simulators ('676/'008) are flat-netlist transistor-level analyzers; the '845 patent is a noise-estimation tool for an already-hierarchical netlist; the RC-reduction papers are numerical-reduction techniques; the manuals/tutorial are background.

Characterization of the references:

• Anticipation (§ 102): none of the cited references anticipates any of claims 1–48.
• Obviousness (§ 103): US 6,665,845 (in view of the RC-reduction literature) is the strongest candidate for a § 103 challenge aimed at the cross-coupling-capacitor and RC-subcircuit optimization features (claims 2–3, 6, 9 and their system/CPP counterparts); US 5,446,676 and US 5,553,008 are, at most, secondary references for the netlist/subcircuit context; the Pillage/Kerns/Feldman trio supports the RC-equivalence reduction of claim 6.
• Related, not prior art: the two co-owned Cadence applications (10/724,277 → US 7,181,383; and 10/993,687) are incorporated by reference / same-day filings and should be treated as part of the disclosure, not as § 102 art.

Confidence caveat: I could verify the three patent citations and the citation lists directly from the USPTO-derived Google Patents record. I could not retrieve the full text of the co-pending application 10/993,687 ("Electrical Isomorphism") or an authoritative USPTO PatentCenter page within the search budget, so my characterization of that item rests on the patent's own statement of it plus its filing date; I flag it as lower-confidence rather than asserting its content.

I'll ground this analysis in the prior-art references of record before building the § 103 combinations.

Obviousness Analysis — US 7,272,805 B2 under 35 U.S.C. § 103

Method note. This analysis uses the prior-art set disclosed in the "Prior Art" sections of the fetched Google Patents page for US 7,272,805 (https://patents.google.com/patent/US7272805/en): the Patent Citations table (3 patents) and the Non-Patent Citations table (8 items). Where a reference is the applicant's own co-pending work I say so explicitly, because that changes whether it is prior art at all — a threshold issue the examiner would have had to resolve before reaching § 103. I have not retrieved the file wrapper or the reasons for allowance, so statements about what the examiner did or did not consider are inference, not record.

I am also flagging a source inconsistency in the page itself: the first "Citations (2)" block lists only US 5,446,676 and US 6,665,845, while the later "Patent Citations (3)" table lists all three (adding US 5,553,008). I treat the three-patent table as authoritative, consistent with the previously generated summary.

1. Legal framework

The application was filed 2004-11-19, so pre-AIA § 103(a) governs, including pre-AIA § 103(c) (common-ownership disqualification, which since the 1999 AIPA amendment reaches § 102(e) art). The Graham v. John Deere factors control: scope/content of the prior art; differences between the prior art and the claims; level of ordinary skill; and secondary considerations. Under KSR Int'l v. Teleflex (2007), a combination is obvious where (a) the references teach or suggest each element, (b) the combination is of familiar elements performing their established functions yielding predictable results, (c) a known technique is used to improve a similar device in the same way, or (d) the design is a predictable variation / "obvious to try" with a reasonable expectation of success. The level of ordinary skill here is high — a person with an M.S./Ph.D. in EE/CS plus several years of EDA tool development (Simulation/Extraction), circa 2004 — which widens the scope of "prior art elements" a PHOSITA would consider combinable.

2. What each reference of record actually supplies

Gap in the record as cited: none of the three cited patents converts a flat parasitic netlist into a hierarchical netlist. '676/'008 consume netlists; '845 analyzes an already-hierarchical netlist. The only record item squarely directed at identifying redundant subcircuits is 10/724,277 — which carries the § 103(c) problem. That gap is the crux of any defense and is why the office action (whatever it was) almost certainly leaned on a combination plus "official notice" of routine programming.

3. Claim 1 — element mapping for the primary combination

Combination A: US 6,665,845 + US 5,446,676 (or US 5,553,008) + 10/724,277 (or, in the alternative, the general knowledge of hierarchy-extraction).

Motivation to combine (KSR prongs (a)–(d)). All three references address the same recognized problem recited in the '805 background: post-layout back-annotated designs contain enormous numbers of parasitic R/C elements, so "the performance of the simulation suffers significantly" and "simulating the flat netlist requires more memory." '845 says the tool must be "faster and less memory intensive than ... SPICE" and that reducing extraction/reduction computer time is desirable; 10/724,277 says the hierarchical data structure "uses less memory and produces better performance"; '676/'008 tout "simulation performance and capacity close to that of gate level logic simulators." That is the classic KSR "design incentive / market pressure" motivation, plus the "known technique (hierarchy) to improve a similar device in the same way" rationale. Secondary indicia unavailable or weak: the '805's own stated advantages (fewer components to simulate, improved performance) are precisely the expected, result-effective benefits of folding a design into reusable subcircuits — a weak nexus.

Reasonable expectation of success. Hierarchical SPICE (.SUBCKT), hierarchical extraction, and hierarchical simulation were each established by 2004 ('845 FIGS. 7–8; '676 modelfile; 10/724,277). A PHOSITA would expect folding + RC reduction (Kerns; Feldman) to preserve electrical behavior within tolerance, which is exactly what claim 6 requires.

4. Secondary combinations targeting specific claim groups

Combination B — '845 + Kerns/Feldman/Pillage (RC reduction). Renders claims 6, 22, 38 obvious: "optimizing the RC subcircuit for creating a corresponding electrically substantially equivalent RC subcircuit having fewer resistor or capacitor elements" is the express subject matter of Kerns et al. (title) and is illustrated in '845 FIGS. 9→10. Motivation: reduce the matrix/network size before noise or timing computation — the references state this benefit.

Combination C — '845 + 10/724,277 (isomorphism test). Renders claims 8, 24, 40 obvious with an unusually tight fit:

I should be candid that this near-verbatim overlap cuts both ways: it makes claims 8/24/40 vulnerable if 10/724,277 is available as prior art, but if it is disqualified under § 103(c) — and if it is treated as mere incorporated-by-reference subject matter rather than a printed publication — the isomorphism test's only record support weakens considerably.

Combination D — '845 (lumping/combining) for claims 9, 25, 41. "Determining a sum of expected cross-coupling capacitance at each node; determining a sum of arrived cross-coupling capacitance; ... compute an average capacitance." '845 discloses summing/lumping coupling capacitances at the ends of a victim line and combining multiple aggressors into single aggressors, which is the same normalization operation applied per node. Motivation: '845 expressly trades per-aggressor precision for tractability. The residual difference — averaging expected vs. arrived Cross-CC per node across an isomorphic net collection — is, on this record, best characterized as a routine arithmetic refinement of a known lumping step ("predictable variation," KSR).

Claims 5, 7, 10–16, 21, 23, 26–32, 37, 39, 42–48 (the algorithmic machinery). These recite NCset arrays, placeholder creation, splitting a subcircuit when more than one upper call path exists, "stitching," port/node creation, and level-counter bookkeeping. Nothing in the record expressly teaches "stitching" a flat netlist into a folded hierarchy — but these limitations are largely data-structure bookkeeping on a general-purpose computer, and KSR authorizes rejection where the claim is "a combination of familiar elements according to known methods" yielding predictable results, or where the limitation is an "obvious to try" design choice among a finite number of identified, predictable solutions. The strongest sub-argument against the applicant here is that splitting a subcircuit to preserve multiple call paths is the necessary consequence of representing one definition used with different port sets — a requirement dictated by the problem, not an inventive contribution. Expect this group to be the hardest to sustain in a rejection and the most likely locus for applicant argument.

5. Claims 17 and 33

Both are mirror images of claim 1. Claim 17's preamble (processing unit, user interface for entering a netlist / viewing representations / observing simulation results, memory) is met literally by US 5,553,008 claim 1: "In an appropriately programmed digital computer having a CPU, memory, user interface and printer ...." The "means for ..." limitations are § 112 ¶ 6 counterparts of claim 1's steps; on the same combinations they are obvious a fortiori because the corresponding structure is a general-purpose computer programmed to perform the recited steps (In re Alappat-type reasoning; KSR on general-purpose computers). Claim 33 is a Beauregard-style product claim whose only additional limitation is a "medium storing computer programs" — a conventional carrier at the 2004 priority date; obviousness rises or falls with claim 1.

6. Defenses the patent owner would raise (and how strong they are)

1. Reverse-direction gap / no express teaching of flat→hierarchical. Every cited reference either consumes a netlist or assumes a hierarchical one; the record's "flattening" flows the opposite direction. This is the strongest non-obviousness argument. Counter: KSR rejects the requirement of an express teaching or "teaching, suggestion, or motivation"; the motivation comes from the articulated performance/memory problem common to all references. Strength: medium. It would likely defeat a rejection built only on the three cited patents, but not one that adds 10/724,277 or that takes official notice of hierarchy extraction (Beatty & Bryant 1988; Wong, "Hierarchical Circuit Verification," DAC 1985 — the latter is itself cited on the face of US 7,181,383 and would be devastating here if the examiner reached for it).
2. § 103(c) common-ownership disqualification of 10/724,277. It is commonly owned Cadence art, filed 2003-11-26, qualifying at most under § 102(e). Pre-AIA § 103(c) (as amended by the 1999 AIPA) excludes exactly such art from § 103. If the applicant filed a common-ownership statement, the only record reference squarely teaching isomorphism identification drops out. Strength: potentially high; I flag it as the single most important unresolved issue.
3. Incorporation-by-reference is not prior-art status. The '805 specification incorporates 10/724,277 "expressly by reference." Incorporated material is generally available for § 112 support but is not thereby converted into prior art; it must independently qualify. Strength: medium (and it partly conflicts with the § 103(c) argument — the same reference is both "ours" and "not theirs").
4. 10/993,687 ("Electrical Isomorphism") is not prior art at all. Same-day filing, same inventive entity, commonly owned. Any rejection relying on it would be improper. Strength: high, but it probably was not the basis of allowance.
5. Secondary considerations. None are of record; the '805's asserted benefits (fewer simulated components, better performance) are the expected consequence of hierarchy, and under KSR an expected advantage in the use of a known technique is weak evidence of non-obviousness. Strength: low.
6. Arguable claim-drafting idiosyncrasies. Claim 5(c) recites an "anchor node ... referenc[ing] one or more subcircuits having substantially the same isomorphic behaviors," and claim 13(e) says "reconnecting elements of late subcircuit" (the fetched text's "late" appears to be a transcription artifact). These § 112 irregularities do not defeat a § 103 rejection but complicate mapping.

7. Bottom line

Overall: US 7,272,805 is not clearly obvious on the three cited patents alone, because the record contains no teaching of flat→hierarchical conversion. It becomes substantially more vulnerable the moment the analysis adds (i) the applicant's own co-pending 10/724,277 for isomorphism identification and the anchor-node hierarchy — subject to the § 103(c) common-ownership objection, which I judge the decisive open issue — and (ii) the RC-reduction NPL of record plus the background on hierarchical SPICE. The claims most likely to fall are 6/22/38 and 8/24/40; the claims most likely to survive are the split/stitch algorithm claims (10–16, 26–32, 42–48).

8. Confidence and explicit uncertainties

• High confidence in the parallel quoted above between '805 claim 8 and the "Dynamic Isomorphic Partitioning" definition in US 7,181,383 (https://patents.justia.com/patent/[7181383](/patent/7181383)); both are quoted from live sources retrieved today.
• High confidence in what US 5,446,676 / US 5,553,008 disclose (netlists, subcircuits, CPU/memory/user-interface preamble, RC elements): https://patents.google.com/patent/[US5446676A](/patent/US5446676A), https://patents.google.com/patent/[US5553008A](/patent/US5553008A).
• High confidence in US 6,665,845's coupling-capacitor/lumping/hierarchical-netlist disclosure: https://patents.google.com/patent/US6665845.
• Medium confidence on the pre-AIA § 103(c) disqualification of 10/724,277: the legal rule is settled, but application depends on facts I have not verified — whether a common-ownership statement was filed, the exact 102(e) dates, and the inventorship overlap. I did not review the file wrapper, assignment records, or PatentCenter.
• Not verified: the examiner's actual reasons for allowance; any PTAB proceeding; whether any non-record art (e.g., Nassda's US 6,577,992 "Transistor level circuit simulator using hierarchical data," Synopsys' US 6,807,520, Beatty & Bryant 1988, or Wong DAC 1985) was before the examiner. Those references appear in the other Cadence patent's citation record, not in the '805 record, and I cite them here only as supplementary context — not as part of the '805 "Prior Art" section you directed me to.
• This is a technical validity assessment, not a legal opinion; given the patent expired for non-payment of maintenance fees (per the Legal Events), the practical stakes of any § 103 conclusion are historical/portfolio-related rather than enforcement-related.