Prior art

To identify the most relevant prior art for US patent 7238550, I will examine the "Patent Citations" section of the patent document. This section lists patents that were cited by the examiner or by third parties during the prosecution of US7238550.

Here is an analysis of the most relevant prior art cited in US7238550:

Most Relevant Prior Art for US7238550

1. US6119049A

   • Full Citation: US6119049A - Memory module assembly using partially defective chips.
   • Publication/Filing Date: Publication Date: September 12, 2000; Filing Date: August 12, 1996.
   • Brief Description: This patent describes a memory module assembly that utilizes partially defective memory chips. It focuses on methods for patching these defective chips to create a functional module. The patent is directly referenced multiple times within US7238550, particularly in the context of patching processes for Chip-on-Board modules.
   • Potential Anticipation (35 U.S.C. § 102): US6119049A potentially anticipates elements of claims related to using partially defective memory parts and patching techniques. For instance, claims 7 and 17, which describe methods of fabricating Chip-on-Board logic modules, involve mounting logic parts and potentially patching them. The concept of utilizing partially-defective parts (as mentioned in the abstract of US7238550) is also a core aspect of US6119049A. The background section of US7238550 explicitly states, "While the process used to assemble Chip-on-Board modules, referring to the process disclosed in U.S. Pat. No. 6,119,049, is effective, modern adhesives provide new methods of mounting unpackaged parts." This indicates that US6119049A covers the general concept of COB assembly with defective chips, while US7238550 aims to improve upon the mounting process. Therefore, the core concept of assembling memory modules from partially defective chips, and the patching aspect of such, could be anticipated.

2. US5866953A

   • Full Citation: US5866953A - Packaged die on PCB with heat sink encapsulant.
   • Publication/Filing Date: Publication Date: February 2, 1999; Filing Date: May 24, 1996.
   • Brief Description: This patent describes a packaged die mounted on a Printed Circuit Board (PCB) with a heat sink encapsulant. It addresses packaging and thermal management for semiconductor devices.
   • Potential Anticipation (35 U.S.C. § 102): This patent could potentially anticipate aspects of claims related to the encapsulation or covering of electronic components on a PCB. Specifically, claims 1, 7, and 17 involve steps of covering layers of settable material and capturing bonding wires. While US5866953A describes a "heat sink encapsulant" for packaged dies, the general concept of encapsulating or covering a die on a PCB could be considered. Claim 38 of US7238550 describes "placing a cover over said unpackaged die and attaching said cover a circuit board on which said unpackaged die is mounted, said cover not being in direct contact with said unpackaged die." The idea of a protective covering is present in both, although the specifics (heat sink vs. non-heat sink, packaged vs. unpackaged) differ.

3. US6238951B1

   • Full Citation: US6238951B1 - Process for producing a sealing and mechanical strength ring between a substrate and a chip hybridized by bumps on the substrate.
   • Publication/Filing Date: Publication Date: May 29, 2001; Filing Date: May 28, 1993.
   • Brief Description: This patent details a process for creating a sealing and mechanical strength ring between a substrate and a chip that is connected by bumps.
   • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant to claims 1, 7, and 17 of US7238550, especially regarding the use of a "ring" of settable material. Claim 1 explicitly mentions "hardening a ring of said first layer of selectively-settable material around a periphery said unpackaged die." Similarly, claim 7 refers to "selectively hardening areas of a selectively settable material," which could encompass a ring, and claim 13 specifically states, "wherein said selectively hardening areas of said selectively settable material comprises hardening a ring of selectively settable material around said unpackaged logic part". The core idea of forming a hardened ring of material around a chip for securing it to a board, as described in US6238951B1, could be seen as anticipating these aspects.

4. US5477611A

   • Full Citation: US5477611A - Method of forming interface between die and chip carrier.
   • Publication/Filing Date: Publication Date: December 26, 1995; Filing Date: September 20, 1993.
   • Brief Description: This patent describes a method for forming an interface between a die and a chip carrier.
   • Potential Anticipation (35 U.S.C. § 102): This patent could anticipate the general concept of mounting a die to a substrate or carrier. Claims 1, 7, 17, and 25 all pertain to mounting unpackaged dies on a circuit board using selectively settable materials. While the specific "selectively settable materials" and the multi-layer approach of US7238550 might be distinct, the fundamental act of "mounting" and forming an "interface" between a die and a board is a shared concept.

5. US6569709B2

   • Full Citation: US6569709B2 - Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods.
   • Publication/Filing Date: Publication Date: May 27, 2003; Filing Date: October 15, 2001.
   • Brief Description: This patent describes assemblies of stacked semiconductor devices where adhesive material is interposed between them to define separation.
   • Potential Anticipation (35 U.S.C. § 102): This patent could potentially anticipate the use of adhesive material as a "physical and thermal buffer" between a die and a circuit board, as described in claims 4, 5, 17, 21, 23, 25, 28, and 30 of US7238550. Specifically, claim 4 of US7238550 states, "further comprising placing selectively settable material between said unpackaged die and said printed circuit board to provide a physical and thermal buffer." US6569709B2's use of interposed adhesive for separation and assemblies, even in a stacked configuration, suggests a similar functional outcome of providing a buffer.

This analysis focuses on direct citations from the patent itself. A more exhaustive prior art search would involve a broader search for non-patent literature and additional patent families.