Obviousness

Obviousness under 35 U.S.C. § 103 requires an analysis of whether the claimed invention, as a whole, would have been obvious at the time the invention was made to a person having ordinary skill in the art (POSA) in light of the prior art. An invention is considered obvious if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious to a POSA. This analysis typically involves identifying the scope and content of the prior art, ascertaining the differences between the prior art and the claimed invention, and resolving the level of ordinary skill in the pertinent art. A motivation to combine references must be articulated.

The priority date of US Patent 7238550 is February 26, 2002. Therefore, any prior art considered for obviousness must have an effective filing date before this date.

The present patent (US7238550) explicitly states that "modern adhesives provide new methods of mounting unpackaged parts. In particular, an improvement in the yield of Chip-on-Board memory modules can be attained by using one or more selectively settable liquids" and identifies a problem where a standard burn-in process "may frequently cause a number of failed and broken chips, due mostly to a difference in the thermal expansion coefficients of the chips and the circuit board base." This background provides a clear motivation for a POSA to combine existing COB fabrication methods with known adhesive technologies to address these issues.

Person Having Ordinary Skill in the Art (POSA):
A POSA in the field of Chip-on-Board (COB) module fabrication at the time of the invention (February 2002) would likely have a bachelor's degree in electrical engineering, materials science, or a related field, along with several years of experience in semiconductor packaging, assembly processes, and knowledge of adhesives and encapsulants used in electronics.

Obviousness Analysis of Independent Claims

Claim 1: Method of fabricating Chip-on-Board logic modules using selectively settable materials

Claim 1 recites a method comprising:

1. Mounting unpackaged die using a first layer of selectively-settable material.
2. Hardening a ring of said first layer of selectively-settable material around a periphery said unpackaged die.
3. Covering said first layer of selectively-settable material with a second layer of selectively-settable material.
4. Capturing bonding wires connecting said unpackaged die to a printed circuit board in said second layer of selectively-settable material.

Combination of Prior Art:
A combination of US Patent 6,119,049 (Peddle), US Patent 6,238,951 B1 (Commissariat A L'energie Atomique), and US Patent 5,962,810 A (Amkor Technology, Inc.) would render Claim 1 obvious.

• US Patent 6,119,049 (Peddle): This patent teaches the fundamental concept of fabricating Chip-on-Board (COB) memory modules, specifically utilizing unpackaged, partially-defective memory chips. It describes the overall process of mounting such chips to a circuit board and subsequently patching them to achieve a functional module. This reference establishes the broad context of COB memory module assembly.
• US Patent 6,238,951 B1 (Commissariat A L'energie Atomique): This patent describes a process for producing a sealing and mechanical strength ring of curable resin between a substrate and a chip. It explicitly teaches applying a "ring of curable resin" around the periphery of a chip and hardening this ring. This directly addresses the "hardening a ring of said first layer of selectively-settable material around a periphery said unpackaged die" step of Claim 1.
• US Patent 5,962,810 A (Amkor Technology, Inc.): This patent discloses an integrated circuit package that employs a transparent encapsulant. It teaches forming an encapsulant body over a semiconductor die and its bonding wires for protection. This teaches the concept of covering the die and wires with a protective material, analogous to the "covering said first layer... with a second layer... and capturing bonding wires... in said second layer" of Claim 1, albeit with a single encapsulant.

Motivation to Combine:
A POSA in February 2002, when attempting to improve the COB module fabrication process taught by US Patent 6,119,049 to enhance reliability and protect the delicate unpackaged dies and bonding wires, would be motivated to incorporate known techniques for die attachment and encapsulation. The specific problem of managing the physical connection and protection of fine bonding wires is a well-recognized challenge in COB assembly.

The POSA would consider applying a curable adhesive for mounting and protecting the unpackaged die and wires. US Patent 6,238,951 B1 explicitly teaches forming a hardened resin ring around the chip for mechanical strength, which directly suggests using a selectively-settable material to tack the unpackaged die in place on the PC board, as in the second step of Claim 1. Subsequently, to protect the fragile bonding wires, a POSA would find it obvious to apply another layer of encapsulant over the die and wires, as taught by US Patent 5,962,810 A. The sequential application of a first ring for tacking and a second layer for capturing wires offers improved control during manufacturing, allowing for wire bonding after the initial die placement and before final encapsulation. This is a logical refinement of known encapsulation practices, driven by the desire for improved process control and enhanced protection of the module.

Claim 7: Method of fabricating a Chip-on-Board logic module

Claim 7 recites a method comprising:

1. Mounting one or more electronic logic parts on a printed circuit board using said selectively settable materials.
2. Selectively hardening areas of a selectively settable material.
3. Attaching bonding wires between pads of said logic parts and pads of said printed circuit board.
4. Applying selectively settable material to cover a portion of each of said bonding wires.
5. Then, inspecting bonding wire connections.
6. Readjusting bonding wires, if needed.
7. Hardening said selectively settable material that covers said bonding wires.

Combination of Prior Art:
A combination of US Patent 6,119,049 (Peddle), US Patent 5,962,810 A (Amkor Technology, Inc.), US Patent 6,238,951 B1 (Commissariat A L'energie Atomique), and general knowledge of quality control and rework in semiconductor manufacturing would render Claim 7 obvious.

• US Patent 6,119,049 (Peddle): Provides the context of fabricating COB memory modules with unpackaged chips and the overall assembly and testing process.
• US Patent 5,962,810 A (Amkor Technology, Inc.): Teaches forming a transparent encapsulant over a die and bonding wires for protection.
• US Patent 6,238,951 B1 (Commissariat A L'energie Atomique): Teaches selectively hardening a ring of curable resin around a chip, exemplifying "selectively hardening areas of a selectively settable material."
• General Knowledge/Industry Practice: The steps of "inspecting bonding wire connections" and "readjusting bonding wires, if needed" are routine quality assurance and rework procedures in semiconductor device assembly. The patent itself confirms this, stating that after wires are bonded, "a visual inspection of the wires is made (step 106). If there are any missing or broken wires (determination 107), a manual adjustment of the bonds (step 108) is used to correct the problem." Commercially available machines for bonding wire installation are also generally known in the art.

Motivation to Combine:
A POSA, aiming to implement a robust and reliable COB fabrication process (as generally taught by US Patent 6,119,049), would be motivated to integrate well-known techniques for die attachment, wire bonding, encapsulation, and quality control. The use of "selectively settable materials" (as taught by US Patent 6,238,951 B1 regarding curable resins, and generally for other adhesives) offers the advantage of precise control over the curing process, enabling the parts to be mounted and temporarily secured before final hardening.

The problem of potentially faulty bond wires is inherent in wire bonding processes. Therefore, a POSA would find it obvious to include standard inspection steps (visual inspection) and, if necessary, rework or "readjusting bonding wires" before fully hardening the encapsulating material. This approach leverages the property of selectively settable materials to remain workable before final hardening, thereby facilitating rework and improving yield. Applying the selectively settable material to cover a portion of the wires and then hardening it (as taught by US Patent 5,962,810 A) is a logical method to secure and protect the bond wires after they have been properly formed and inspected.

Claim 17: Method of fabricating Chip-on-Board logic modules (with unhardened material buffer)

Claim 17 recites a method comprising:

1. Mounting unpackaged die on a circuit board using a first layer of selectively-settable material.
2. Hardening a portion of said first layer of selectively-settable material such that said unpackaged die is secured to said circuit board, but some of said selectively-settable material between said unpackaged die and said circuit board is never fully hardened.

Combination of Prior Art:
A combination of US Patent 6,119,049 (Peddle), US Patent 6,238,951 B1 (Commissariat A L'energie Atomique), US Patent 6,784,555 B2 (Dow Corning Corporation), and US Patent 5,866,953 A (Micron Technology, Inc.), combined with the common understanding of thermal stress management in semiconductor packaging, would render Claim 17 obvious.

• US Patent 6,119,049 (Peddle): Establishes the COB fabrication context.
• US Patent 6,238,951 B1 (Commissariat A L'energie Atomique): Teaches applying and hardening a ring of curable resin around a chip for mechanical strength. This demonstrates selective hardening to secure a die while implicitly leaving the area under the die free or containing unhardened material if only a perimeter ring is cured.
• US Patent 6,784,555 B2 (Dow Corning Corporation): This patent describes die attach adhesives, many of which are polymeric and can have varying curing characteristics. The general knowledge of different curing temperatures or wavelengths for various components within the same material (e.g., UV materials with different hardening levels based on wavelength, as mentioned in US7238550) would be understood by a POSA.
• US Patent 5,866,953 A (Micron Technology, Inc.): This patent teaches a packaged die on a PCB with a heat sink encapsulant. It discloses the use of encapsulants around a die, implying the presence of material between the die and the PCB, and the protective role of such materials.

Motivation to Combine:
The patent itself clearly articulates the problem that motivates this claim: "A standard burn-in process used to test electronic memory modules... may frequently cause a number of failed and broken chips, due mostly to a difference in the thermal expansion coefficients of the chips and the circuit board base." The patent further states that "the uncured adhesive liquid that remains under a select memory die serves as a thermal and physical buffer between the die and the PC board. This buffer may be valuable during the burn-in test to prevent damage to the unit caused by unequal thermal expansion coefficients of the die and the PC board."

A POSA, confronted with the known issue of thermal expansion mismatch during burn-in in COB modules (as noted in US7238550), would be motivated to introduce a compliant or buffering layer between the unpackaged die and the rigid circuit board. Given the availability of various selectively settable adhesives (such as those described in US Patent 6,784,555 B2) and methods for selective curing (like the ring hardening in US Patent 6,238,951 B1), it would be obvious to apply an adhesive material under the die. A POSA would then selectively harden only the periphery of this material (e.g., as a ring) to secure the die, while deliberately leaving the material directly beneath the die in a less cured (e.g., liquid or gel-like) state. This less-cured material would then serve as a physical and thermal buffer, mitigating stress caused by differential thermal expansion, a known engineering solution to a known problem. The explicit mention in US7238550 of UV materials having different hardness levels depending on wavelength highlights a recognized method for achieving such selective or partial curing.

Claim 25: Chip-on-Board logic module (product claim)

Claim 25 recites a module comprising:

1. A circuit board.
2. An unpackaged die mounted on said circuit board using a first layer of selectively-settable material, wherein a portion of said first layer of selectively-settable material has been hardened such that said unpackaged die is secured to said circuit board, but some of said selectively-settable material between said unpackaged die and said circuit board is never fully hardened.

Obviousness of Claim 25:
As Claim 25 describes a product that inherently results from the method described in Claim 17, if the method of Claim 17 is obvious, then the product of Claim 25 would likewise be obvious. The structural features recited in Claim 25 (a circuit board, an unpackaged die mounted with a first layer of selectively-settable material, a hardened portion securing the die, and some unhardened material between the die and the board) are directly realized by performing the method steps of Claim 17, which, as analyzed above, is obvious when combining US Patent 6,119,049, US Patent 6,238,951 B1, US Patent 6,784,555 B2, US Patent 5,866,953 A, and general engineering knowledge. Therefore, the resulting structure would also be obvious.