US 7165131

I'll search for authoritative information on US patent 7165131, including any litigation or CAFC docket activity.

Let me run additional targeted searches for litigation/PTAB activity and USPTO status.

US Patent 7,165,131 — Analyst Summary

Verification note: The full text I was provided is the authoritative source (Google Patents, fetched 2026‑09‑27 from https://patents.google.com/patent/[US7165131](/patent/US7165131)/en), corroborated by Justia (https://patents.justia.com/patent/7165131) and FreePatentsOnline. I interpreted the number literally and did not substitute any similar identifier.

Bibliographic data

Abstract (verbatim)

"In one embodiment of the present invention, a method may include separating incoming transactions to an agent of a coherent system into at least a first channel, a second channel, and a third channel, based upon a type of the incoming transactions. The incoming transactions may be sent by a peer device coupled to the coherent system. By separating the transactions based on type, deadlocks may be avoided."

Plain‑language overview

Problem addressed: In point‑to‑point architectures (the patent cites PCI Express Base Spec Rev. 1.0, published 2002‑07‑22), peer‑to‑peer traffic between I/O devices must cross secondary protocols and a coherent fabric. PCI‑style I/O uses posted vs. non‑posted ordering rules, and PCI relies on "retry" for forward progress — a mechanism not available where credit tracking occurs at different layers of a different protocol. The stated need is deadlock‑free transfer of transactions across a multi‑protocol system.

Core solution: An agent (e.g., I/O hub, "CSI agent") sorts incoming transactions by type into plural virtual channels/virtual networks that are kept separate (independent flow control, separate credit pools) through the physical, link, and routing layers. An example mapping (Table 1) routes memory writes and peer‑to‑peer writes/messages to a non‑coherent bypass channel (NCB), memory reads and I/O/configuration reads‑and‑writes to a non‑coherent standard channel (NCS), and completions to a completion channel (CMP). A first queue (txn_que) overflows posted transactions to a second queue (byp_que) when backed up; the two queues feed a multiplexer into the CSI transaction layer.

Independent claims (literal scope):

• Claim 1 (method): receiving incoming transactions to an agent of a coherent system in a first input queue; forwarding at least some of the transactions from the first input queue to a second input queue; and separating the incoming transactions into a first virtual network including at least a first, second, and third channel and a second virtual network including a fourth and fifth channel, based on transaction type.
• Claim 11 (article – machine‑accessible storage medium): program instructions enabling a system to perform the same three steps of claim 1 (first queue receive; forward some to a second queue; separate into the two virtual networks based on transaction type).
• Claim 14 (apparatus): a first bus agent with a first input queue, a second input queue receiving at least some transactions from the first, and a multiplexer coupled to the outputs of both queues providing a selected output to a transaction layer that routes transactions via a first virtual network including at least three channels or a second virtual network including at least three other channels, based on transaction type.
• Claim 18 (system): a first bus agent (receives into a first queue, forwards some to a second queue, routes queue outputs via the first or second virtual network based on type) and a second bus agent coupled to the first via a point‑to‑point interconnect.

Notable drafting points / uncertainties in the record:

• There is an internal inconsistency among the independents as to the second virtual network: claim 1 recites a "second virtual network including … a fourth channel and a fifth channel," whereas claims 14 and 18 recite a "second virtual network including at least three other channels." A court would need to reconcile these; I cannot resolve it authoritatively from the face of the document.
• Claims 22–26 appear to be a later‑added group (claim 22 depends on claim 1 and re‑uses "the method of claim 1"; claim 23/24 depend on claim 1 but claim 24 refers to "posted transactions"; claims 25 depends on claim 14; claim 26 depends on claim 4). They read as amendments rather than the original set.
• The written description limits the channel architecture by example (standard/bypass/completion), and Table 1 is expressly stated to be non‑limiting ("transactions of another I/O device … may be transmitted on any desired virtual channel").

Litigation / CAFC 2026 docket check

I searched for US 7,165,131 infringement actions, PTAB proceedings, and Federal Circuit 2026 activity.

• No CAFC 2026 docket or opinion involving US 7,165,131 was found. My searches of Federal Circuit 2026 opinion/order summaries and dockets returned unrelated patents (e.g., US 6,821,540; US 10,912,321; US 8,958,853; US 10,664,518; US 10,403,051; US 8,620,413) and no reference to 7,165,131.
• No PTAB (IPR/PGR) proceeding on this patent appeared in results.
• Caution on identifier collisions: the string "7165131" resolves in other corpora to unrelated items — a Japanese patent JP 7165131 B2 (Philip Morris Products, "smoking article with fire‑extinguishing means," issued 2022‑11‑02) and a US trademark registration 7165131 ("HANDLE IT"). These are not US Patent 7,165,131 and must not be conflated.

Confidence: High on bibliographic data, abstract, claims, and status (from the authoritative source). Moderate-to-high that no 2026 CAFC litigation exists — this is a negative finding from my searches, not a definitive certified docket check; I cannot guarantee completeness of third‑party litigation databases. If you need a certified result, a PACER/docket‑specific or Docket Navigator query is warranted.

International family (for context)

Priority applications claiming 2004‑04‑27: TW 093125587 (TWI264904B — status "IP Right Cessation"); KR 10‑2004‑0069652 (KR100715741B1 — expired, fee related); JP 2004‑259773 (JP2005318495A — listed "active/pending" in the source); CN 200410078931.X (CN100524271C — expired, fee related); EP 04256166 (EP1591908A1 — ceased).

Sources: https://patents.google.com/patent/US7165131/en ; https://patents.justia.com/patent/7165131 ; https://FreePatentsOnline.com/y2005/0251612.html ; https://patents.justia.com/patent/20050251612

I'll research litigation involving US patent 7165131 across patent litigation databases.

Initial searches returned no matches for this specific patent. Let me dig deeper into specialized litigation databases.

Let me check the specialized patent litigation portals directly.

Litigation Search Report — U.S. Patent No. 7,165,131

Patent identified: U.S. Patent No. 7,165,131 B2 ("Separating transactions into different virtual channels"), inventors Kenneth C. Creta, Aaron T. Spink, and Robert G. Blankenship; assignee Intel Corporation; filed April 27, 2004; issued January 16, 2007.

Result: No litigation identified

I found no record of any litigation (district court, ITC, or Federal Circuit appeal) involving U.S. Patent No. 7,165,131.

Searches across Google Patents/Justia patent pages, Patent Trial & Appeal Board dockets, Unified Patents, Docket Alarm, CourtListener, and general litigation news surfaced only the following, none of which is litigation:

• Patent citations and forward citations. The citing/cited-by tables on the Google Patents and Justia pages list other patent documents (e.g., AMD's WO2002015470A2, Intel's own US 6,243,781; and later Intel, IBM, and Apple patents citing it). These are patent references, not court cases, and should not be mistaken for litigation.
• One PTAB submission mentioning the number. Patent No. 7,165,131 appears in an examiner search-strategy string in a PTAB proceeding (petition document, USPTO PTACTS, query "("7165131")...PN."). That is a prior-art/patentability search artifact, not an assertion of the patent in litigation.

Cautionary note on false positives

Because the rule is to interpret identifiers literally, I flag that other, unrelated matter shares this number and should not be attributed to this patent:

• JP 7165131 B2 — a Japanese patent (特許第7165131号) owned by Philip Morris Products S.A. for a smoking article with fire-suppression means. Different jurisdiction, different subject matter, different family.
• A Lithuanian business-registry notice referencing "Pranešimo Nr. 7165131" — an unrelated administrative number.

These arithmetically similar identifiers are not U.S. Patent No. 7,165,131 and are excluded.

Status of the patent (for context)

Per the authoritative full text provided (Google Patents, fetched 2026-09-27):

• Maintenance-fee lapse: "PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES," effective January 16, 2019 (lapse recorded February 18, 2019).
• Adjusted expiration listed as December 25, 2024; legal status "Expired – Fee Related."
• Foreign counterparts in the family: EP 1591908A1 (ceased), KR 100715741B1 (expired/fee related), CN 100524271C (expired/fee related), TW I264904B (IP right cessation), JP 2005318495A (listed as active/pending).

Bottom line: Consistent with the patent's 2019 lapse for non-payment of maintenance fees and its issuance to Intel (a large operating company that was not a frequent patent plaintiff on this particular portfolio), there is no known litigation involving U.S. Patent No. 7,165,131. Because Unified Patents, Docket Alarm, and PACER were not fully queried (search limits were reached), this conclusion is based on the sources actually retrieved and should be treated as a good-faith null result rather than a certified "never litigated" finding.

I'll verify the canonical "no PTAB activity" signal against the live web before writing.

Proceedings overview

Zero AIA trial proceedings are on file for US 7,165,131. The structured USPTO Open Data Portal block states no AIA trial proceedings (IPR, PGR, or CBM) exist for this patent as of the most recent ingest, and my independent web searches surfaced no petition, institution decision, Final Written Decision, or Federal Circuit appeal naming US 7,165,131 — so the breakdown is 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution-denied, and the defensive posture is not "hardened patent" and not "kill-shot IPR precedent"; it is "untested claims plus a fee-lapse expiry," meaning the strongest defenses here are temporal (the patent term appears to have ended) rather than PTAB-based.

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No proceedings to report

There is no proceeding number to recite, and I will not invent one. For completeness, here is what the null result means and how I verified it:

False-positive warning — do not confuse these with US 7,165,131. My searches repeatedly returned same-numbered different patents, and a defendant or a paralegal doing a quick docket sweep will hit these too:

• US 6,717,513 — a different patent, challenged in Unified Patents v. ..., IPR2021-01452 line of filings (the "message profile"/Shetty–Joao obviousness petition). Not this patent.
• US 9,912,513 — Atlas Global Technologies' Wi-Fi trigger-frame patent asserted against Sercomm/ASUS. Different patent, different owner (Atlas, not Intel), different technology.
• JP 7165131 — a Japanese smoking-article patent (Philip Morris). Pure number collision, opposite technical field.

None of those are proceedings against the patent in suit. Reporting them as 7,165,131 proceedings would be a fabrication-by-Ctrl-F error, which is exactly the kind of thing that gets a defendant sanctioned for a bad IPR-filing rationale.

Related context on the '131 family

The patent's own front page lists two co-pending sibling applications, which are applications, not PTAB proceedings:

• U.S. Appl. No. 10/832,606, filed 2004-04-27, "Globally Unique Transaction Identifiers."
• U.S. Appl. No. 10/832,607, filed 2004-04-27, "Transmitting Peer-to-Peer Transactions Through a Coherent Interface" (published as US20050251611A1, Creta et al.).

That family was never litigated into an IPR either, so far as the record shows — consistent with 7,165,131 being an Intel-prosecuted platform patent rather than an Intel-asserted one.

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Strategic summary

Claim status: all 26 claims are UNTESTED. No claim of US 7,165,131 — independent claims 1, 11, 14, and 18, or any of their dependents — has ever been canceled, confirmed, or even construed by the PTAB in an AIA trial. There is no FWD to lean on, no claim-level disposition to quote, and no narrowing amendment. For a defendant, that cuts both ways: there is no "claims 1–5 are dead" argument available, but there is also no Patent Owner precedent establishing that the claims are valid over art — the validity record is a blank slate.

Estoppel landscape: clean. Because no IPR/PGR was ever instituted against this patent, § 315(e)(2) estoppel does not attach to any party. No petitioner is barred from raising any ground, and neither is any privy or real party in interest. If a defendant has been served with a complaint asserting 7,165,131, the only clock that matters is the § 315(b) one-year bar running from service of the complaint (or from service of a complaint alleging infringement of the patent, whether or not it names the same accused product). If the defendant has not been served, there is no bar at all and the full universe of § 102/§ 103 art — plus § 112 written-description and indefiniteness theories, which are the natural attack on the "virtual network ... first channel ... second channel ... third channel" claim language given the specification's own admission that the channel count is flexible — remains open. Note the counterweight: the patent's 2004 priority date means the art pool is 2004-and-earlier Ethernet/InfiniBand/PCI-X/coherent-hub routing literature, which is well-trodden (see the Intel and AMD/Newisys references cited on the face of the patent), so invalidity art likely exists — but nobody has ever tested it.

Pattern signals: none of the usual tells. No serial petitioner, no defensive aggregator (no Unified Patents, RPX, or PQA involvement anywhere in the record), no Director Review, no ex parte reexam, and no CAFC appeal. Intel is the original and current assignee with no recorded reassignment, and the patent was never part of the NPE-transferred portfolios (VLSI, Fortress, etc.) that generated the big Intel IPR waves. The structural explanation for zero IPRs is straightforward: nobody ever needed one, and § 315(b) never triggered because the patent appears not to have been asserted.

The real defense is the calendar, not the Board. Two dates dominate any current analysis:

1. Fee lapse (recorded). The legal-events record shows a maintenance-fee reminder mailed 2018-09-03, then on 2019-02-18 an event coded LAPS — "PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES" — and an STCH entry, "PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362," with effective date 2019-01-16. If that lapse was never cured by petition/revival or by payment of the surcharge, the patent was not enforceable for the last ~five years of its nominal life.
2. Nominal term. The same Google Patents record also shows legal status "Expired – Fee Related" with an "adjusted expiration" of 2024-12-25 (20 years from the 2004-04-27 filing plus PTA). Those two entries are in tension: the adjusted-expiration field reflects the term as if all maintenance fees had been paid, while the LAPS/STCH events reflect that they were not. If the patent was revived, the term runs to 2024-12-25; if it was not, it ended 2019-01-16.

I want to be explicit about my confidence here: I am reading the Google Patents legal-events mirror, not the USPTO PatentCenter fee/revival history itself, and I did not find a recorded revival or a petition decision. Confirm the lapse/revival status directly in PatentCenter (or USPTO PatentCenter) before relying on it — because if the lapse stands, it is dispositive and it is the single most valuable fact in this entire report.

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Recommended next steps

• No PTAB activity exists, and I am saying that plainly. Do not file an IPR on the assumption that a prior petition or FWD exists — there is no § 315(e)(2) estoppel tying anyone's hands, and no earlier panel reasoning to build on. A fresh petition would be a first-instance challenge.
• Pull the fee/revival record first, before spending on prior art. The recorded effective expiration date of 2019-01-16 (event code LAPS, "PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES," 37 C.F.R. § 1.362) is the highest-leverage item on this page. If the patent lapsed and was not revived under 35 U.S.C. §§ 41(c)(1)/(c)(2), there is no enforceable patent and the § 286 six-year damages window plus the post-expiration conduct cut-off likely collapses the demand. Get this from USPTO PatentCenter.
• If the patent is live (revived, or the LAPS entry superseded), then the analysis shifts: confirm the 2024-12-25 adjusted-expiration date against the Patent Term Adjustment calculation, apply the § 286 six-year lookback to whatever complaint date you face, and treat the absence of any prior IPR as an invitation. There is no estoppel, no Fintiv history, and no prior-art record to distinguish — a first-filed IPR on the 26 untested claims faces an unusually clear field. Note only that a petition against an expired or nearly-expired patent is still institutable but cannot be met with a claim amendment, and PTAB claim construction of an expired patent uses the Phillips framework.
• Dockets and links to use going forward: PTAB E2E / PTACTS for any future petition, USPTO PTAB Decisions for any FWD, CourtListener for any CAFC appeal, and the Google Patents family page for family/status confirmation. If a petition appears in the future, the mandatory § 316(a)(11) one-year clock runs from institution — but as of 2026-09-27 there is nothing on file, and I found no "older or recently-filed" proceeding that the ODP ingest is merely late in indexing.

I'll verify the assignment record against the USPTO Assignment Center and cross-reference the legal events already in the authoritative text.

Let me verify whether any post-issuance assignment records exist and cross-check the sibling application.

Inventors

Assignee on the face of the patent: Intel Corporation (per the Google Patents bibliographic data in the authoritative text).

Unusual-pattern check — departures: No departure signal. All three inventors assigned to Intel by the same instrument (reel 015269/0685) and each continued to appear as an Intel inventor on later filings (Creta and Blankenship into 2024–2025 per Patent Leaderboard / PatentGuru inventor listings). There is no evidence of inventors leaving within 12 months of the 2004-04-27 filing, and therefore no "abandoned-team precedes a fire-sale" tell. The only anomaly worth recording is procedural: the three inventors executed the assignment on different dates spanning 2004-04-16 to 2004-04-23, i.e., all executed shortly before the 2004-04-27 filing date — the normal pattern for a large-entity corporate filing, not a distress pattern.

Original assignee

Intel Corporation — a Delaware corporation, 2200 Mission College Blvd., Santa Clara, CA 95054 (address form taken from the contemporaneous Intel assignment instrument recorded at reel 22721/237).

• Primary line of business: design and manufacture of microprocessors, chipsets, and platform silicon; at the 2004 filing date Intel was the dominant x86 CPU supplier.
• Product embodying the claims: This is an inference, not a recorded fact. The specification describes transaction separation across virtual channels in a "CSI" (Common System Interface) coherent fabric with NCS/NCB/CMP channels (FIG. 2; claim 1). Intel's CSI program was publicly productized as QuickPath Interconnect (QPI), shipping with Nehalem-generation Xeon/Core processors and their I/O hubs from 2008 — i.e., the patent is plausibly practiced by Intel's own chipset/IOH silicon. I flag this as an engineering-inference mapping from the spec's own terminology rather than a documented product-to-claim chart; I did not locate a record that formally maps this patent to a shipping SKU.
• Current status: Operating. Intel is not acquired, dissolved, or in bankruptcy. The patent (not the company) went dead: the 12-year maintenance fee due 2019-01-16 was never paid, and the USPTO recorded "PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES" on 2019-02-18 (legal events in the authoritative text). Prior fees were paid on time (4-year, 2010-07-08; 8-year, 2014-06-18).

Assignment timeline

One — and only one — recorded assignment exists for US 7,165,131. There are no post-issuance conveyances, no security agreements, no name-change records, and no merger records in the chain.

• 2004-04-16 → 2004-04-23 (executed, per inventor-specific signing dates) / recorded 2004-04-27 — Reel 015269/0685
  • Conveyance: Assignment — "ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)." Free-format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CRETA, KENNETH C.;SPINK, AARON T.;BLANKENSHIP, ROBERT G.;REEL/FRAME:015269/0685;SIGNING DATES FROM 20040416 TO 20040423
  • Assignor: Creta, Kenneth C.; Spink, Aaron T.; Blankenship, Robert G. (all three jointly)
  • Assignee: Intel Corporation, Santa Clara, California
  • Correspondent: Not exposed in the sources retrieved. Google Patents' Legal Events table (the authoritative text supplied) renders only the recordation code, owner name, reel/frame, and the free-format text above — it does not publish the correspondent/attorney-of-record block. I therefore cannot name the recording correspondent, and I am not going to guess it from Intel's general outside-counsel roster. (For context only, flagged as a cross-reference and explicitly not imputed to this reel: a separate, later Intel assignment — reel 22721/237, recorded 2009-05-21 — lists Blakely, Sokoloff, Taylor & Zafman LLP, 1279 Oakmead Parkway, Sunnyvale, CA 94085 as correspondent. That is a different reel on a different application and carries no evidentiary weight for reel 015269/0685.)
  • Context: Routine inventor-to-corporate assignment at filing (employment/obligation-to-assign). This is the original assignment, not an acquisition or a transfer.

Cross-check against Google Patents legal events (authoritative text): the only assignment-coded event in the entire history is the 2004-04-27 AS (Assignment) entry; everything after it is FPAY (fee payment), FEPP, LAPS, STCH, and FP (lapse events). Nothing resembling a 2019 or later transfer-to-asserter appears.

Related-record note (not an assignment of this patent): the Non-Patent Citations list two co-pending applications filed the same day by the same Intel group — US 10/832,606 ("Globally Unique Transaction Identifiers," Hum et al.) and US 10/832,607 ("Transmitting Peer-to-Peer Transactions Through a Coherent Interface," Creta et al.). These are the sibling filings referenced in the prior litigation section; they are not chain-of-title documents for US 7,165,131 and are excluded from the timeline.

Timeline diagram

timeline
    title Ownership of US 7165131
    2004 : Inventors execute assignment
         : Recorded reel 015269 0685
         : Intel Corporation assignee
    2007 : Patent issued Jan 16
    2010 : 4 year maintenance fee paid
    2014 : 8 year maintenance fee paid
    2019 : 12 year fee unpaid
         : Patent lapsed Jan 16

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The sole recorded conveyance (reel 015269/0685, recorded 2004-04-27) runs into Intel, an operating company, not out to a licensing vehicle. No "IP/Holdings/Ventures/Licensing" assignee ever appears; there is no Delaware or Texas single-purpose LLC anywhere in the record.

2. Known asserter in the chain — not present. The only assignee of record is Intel Corporation. No acquirer appears matching Acacia, Marathon, IV, IPNav, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, or any Spangenberg-linked entity. The chain starts at Intel and ends at Intel.

3. Repeat correspondent across the chain — unclear. There is only one link, so the "recurrence" test cannot be satisfied even in principle; and the correspondent field for reel 015269/0685 is not retrievable from the sources consulted (see timeline entry above). Marked unclear as a data-availability matter, not as a substantive finding.

4. Cascading transfers — not present. A single assignment executed over 2004-04-16/23 and recorded 2004-04-27, with no subsequent links. There is no chain of LLCs, no shared correspondent address, and no sub-24-month sequence to analyse.

5. Pre-litigation transfer — not present. Consistent with the prior litigation section, no infringement suit naming this patent was found. With no suit and no post-2004 assignment, there is no assignment-within-6-months-of-suit event to flag.

6. Bankruptcy fire-sale — not present. Intel did not file Chapter 7/11 in this period; the patent died by maintenance-fee default (lapse effective 2019-01-16, recorded 2019-02-18), not by an estate sale. Note the important distinction: fee lapse produces an unassertable patent, not a transferred one — the patent was never sold or licensed into the market.

7. Privateering — not present. No transfer from Intel to any NPE asserting on Intel's behalf. The direction of travel is the opposite: in the 2019–2020 N.D. Cal. matter, Intel was a plaintiff suing Fortress/VLSI/Uniloc-linked entities over aggregated-portfolio assertion (Intel Corp. and Apple Inc. v. Fortress Investment Group LLC et al., No. 3:19-cv-07651-EMC). Nothing in the reel 015269/0685 record connects US 7,165,131 to that or any comparable arrangement.

8. Defensive aggregator (anti-NPE) — not present. The chain never terminates at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates at Intel, then at the USPTO's lapse register.

Net reading: zero NPE signals are affirmatively present; one signal is undeterminable purely because the correspondent block is not published in the retrieved record. The strongest ownership finding is a negative one — Intel held this patent unencumbered from 2004 until the 2019 fee lapse, and allowed it to go abandoned rather than sell it.

Verdict

Insufficient data (only the original assignment).

Per the rubric, this category covers "no records, or only the original assignment," which is exactly the situation: the USPTO record for US 7,165,131 consists of a single conveyance — inventors Creta, Spink, and Blankenship to Intel Corporation, executed 2004-04-16/23 and recorded 2004-04-27 at reel 015269/0685 — with no subsequent assignment, security interest, name change, merger, or release of any kind. Intel remained assignee of record through issuance (2007-01-16) until the patent lapsed for non-payment of the 12-year maintenance fee effective 2019-01-16, which functionally neutralised the asset without transferring it. I explicitly did not select "Operating-company assertion," because although Intel is an operating company that plausibly practices the claims in its QPI-generation silicon, there is no assertion of this patent on record; and I did not select "Defensive / non-asserting" because the chain never reached a defensive aggregator — the rubric's defining condition for that verdict.

Verification links:

• Assignment Center (USPTO): https://assignmentcenter.uspto.gov/
• Assignment Search abstract for this patent: https://assignment.uspto.gov/patent/index.html#/patent/search/resultAbstract?id=[7165131](/patent/7165131)&type=pat
• Google Patents legal events used as the cross-check: https://patents.google.com/patent/US7165131/en

Caveats: (a) The correspondent/attorney-of-record for reel 015269/0685 is not published in the Google Patents legal-events rendering supplied, and I did not have a successful live retrieval of the Assignment Center abstract page itself, so signal 3 is unresolvable on the evidence gathered rather than affirmatively negative. (b) Intel's product-practice mapping to QPI is an engineering inference from the specification's own "CSI" terminology — I did not locate a source formally charting the claims onto a shipping SKU, and it should not be cited as a documented fact. (c) Consistent with the previously generated litigation section, this remains a good-faith null result on assertion, not a certified "never litigated" finding.

I'll verify the patent record and research each cited reference before mapping them to claims.

Let me verify the remaining key cited references.

Prior-Art Analysis — U.S. Patent No. 7,165,131 B2

Search/verification note. I queried for the literal string 7165131 and confirmed the target is U.S. Patent No. 7,165,131 B2 ("Separating transactions into different virtual channels"), sole U.S. application 10/833,236, filed 2004‑04‑27, issued 2007‑01‑16, inventors Creta/Spink/Blankenship, assignee Intel Corp. I excluded the two unrelated identifier collisions already flagged in the prior sections (JP 特許第7165131号, Philip Morris Products; U.S. Trademark Reg. 7165131 "HANDLE IT"). I was not able to complete a direct PatentCenter/PAIR query — the search budget was exhausted — so the primary source remains the authoritative full text supplied (Google Patents, fetched 2026‑09‑27), corroborated by Justia, FreePatentsOnline, and uspto.report. [Note: the task header says "Current Date: April 26, 2026," while the system date and the fetched source are 2026‑09‑27 — a discrepancy I am flagging, not resolving.]

The 23 patent citations and 2 non‑patent citations below are taken verbatim from the patent's own citation tables, which is the correct corpus for the question asked.

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1. Legal framework (why this matters for the §102 answer)

Because application 10/833,236 was filed 2004‑04‑27, the pre‑AIA version of 35 U.S.C. §102 governs. With a filing-date presumed constructive invention date of 2004‑04‑27, the three relevant subsections break as follows:

Two structural consequences that dominate this analysis:

1. Anticipation requires a single reference disclosing every element of the claim as arranged (no piecing together). A dependent claim cannot be anticipated unless the independent claim it depends from is also anticipated — so if no reference discloses claim 1, no claim depending from claim 1 can be held anticipated by that reference.
2. Several cited items are not §102 prior art at all — they were filed on or after 2004‑04‑27 (and two are commonly owned siblings of the patent itself).

The independent-claim gist (restated as elements, not repeated analysis):

(Contradiction to preserve, not repair: claim 1 says the second virtual network has five channels; claims 14 and 18 say at least three. This internal inconsistency is unresolved on the face of the document.)

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2. Master table — all 23 patent citations + 2 NPL citations

Duplication flag: citations #22 and NPL‑2 are the same application cited twice (once as a pending application, once as its pre‑grant publication). Any "23 references" tally therefore overstates the distinct-art count by one.

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3. Reference‑by‑reference: which claims each could be argued against under §102, and the gap

Below, "§102 candidate" means the reference is textually positioned to be argued against that claim; "Gap" states why full single‑reference anticipation fails.

Tier 1 — The most relevant prior art

(3) US 6,563,831 B1 — Avici Systems (Dally et al.), Router with virtual channel allocation, filed 1997‑08‑22, issued 2003‑05‑13 (§102(b)).
Discloses flits stored "at storage locations assigned to virtual channels," where "the virtual channels and links within the fabric define virtual networks in which congestion in one virtual network is substantially non‑blocking to data flow through other virtual networks," plus arbitration per fabric router to assign packets to VCs.

• §102 candidates: claims 2, 3, 4, 7 (routing different traffic through different channels; separating traffic types so one cannot block another). Structurally, this is the strongest single teaching in the record of "virtual network" as a resource‑isolated grouping of virtual channels.
• Gap: It is an Internet router fabric, not "an agent of a coherent system"; it has no first‑input‑queue → second‑input‑queue overflow mechanism and no multiplexer at queue outputs. Cannot anticipate claims 1, 11, 14, or 18, and therefore cannot anticipate any dependent claim.

(8) WO 02/015470 A2 (AMD/Alpha; U.S. counterpart US 6,950,438 B1) — Separate virtual channels for posted requests, published 2002‑02‑21 (§102(b)); US 6,950,438 §102(e) as of 2000‑08‑17.
This is the closest prior art in the entire cited corpus. Its abstract and specification disclose: (i) plural virtual channels with separate resources/buffers allocated per virtual channel, (ii) a posted‑command virtual channel dedicated to posted requests, separate from the non‑posted‑command virtual channel, (iii) a response virtual channel, (iv) the same VC set applied across coherent and noncoherent fabrics, with the noncoherent link expressly serving an I/O bridge, and (v) "coupon‑based" (credit) flow control per buffer type, expressly to achieve deadlock‑free operation compatible with PCI posted‑write semantics. Its claims recite the second node storing the posted request packet in a first packet buffer dedicated to the posted command virtual channel (claim 6/17) — a per‑channel input buffer.

• §102 candidates (textually): claims 2, 3, 4, 6, 7, 8 (first type on first channel / second type on second channel; "standard/bypass/completion" mapping onto non‑posted / posted / response; maintaining types separate; separate credits; independent flow control; write‑vs‑read type split).
• Gap: No first input queue → forward at least some to a second input queue element, and no multiplexer coupled to both queue outputs. Its packet buffers are per‑VC destination buffers, not a two‑queue overflow structure. Cannot anticipate claims 1/11/14/18 — and therefore cannot anticipate any dependent claim standing alone.
• Practical significance: this reference is the natural primary reference for a §103 obviousness combination with citation #6 (US 6,243,781) for the two‑queue element.

**(6) US 6,243,781 B1 — Intel (Gandhi et al.), Avoiding deadlock by storing non‑posted transactions in an auxiliary buffer…, filed 1998‑12‑03, issued 2001‑06‑05 (§102(b)).**
Discloses an outbound pipe holding posted and non‑posted transactions in FIFO order; when the non‑posted transaction at the head is rejected (Retry), it is moved aside into an auxiliary buffer, and an arbiter selects between the auxiliary buffer's request and the outbound pipe's subsequent transaction. This is the record's clearest teaching of the "first queue → second queue → arbiter/mux" architecture that appears in claim 1 element (B), claim 14's multiplexer, and claims 23–24.

• §102 candidates (textually): claims 1(B) / 14 (multiplexer-or-arbiter element) / 23 (forwarding based on queue state), and arguably the structural core of claim 24.
• Gap — and an important asymmetry: US 6,243,781 moves non‑posted transactions aside. Claim 24 requires forwarding posted transactions from the first queue to the second. So the reference is contrary to claim 24's literal wording, and it discloses no virtual channels or virtual networks whatsoever. Cannot anticipate any claim of 7,165,131.

Tier 2 — Substantively relevant, but narrower or different

(15) US 6,912,612 B2 — Intel (Kapur et al.), Shared bypass bus structure, filed 2002‑02‑25 (§102(e)); pre‑grant pub. US 2003/0163649 A1 (2003‑08‑28, §102(a)).
Coherent scalable switch; a shared bypass bus carries coherency traffic around the crossbar; separate read and write re‑order queues; explicit discussion that I/O devices depend on transaction ordering while the host bus is an "unordered domain." Relevant to claims 4, 23, 24 and to the patent's stated problem. Gap: no by‑type virtual channel/network separation for incoming I/O transactions.

(16) US 7,047,374 B2 — Intel, Memory read/write reordering, filed 2002‑02‑25 (§102(e)). Same Feb‑2002 Intel family as #15. Read/write reordering; relevant to claims 2, 4, 8. Gap: no VN abstraction, no two‑queue overflow.

(12)/(14) US 2003/0041185 A1 / US 6,801,976 B2 — Intel (Creta et al.), Mechanism for preserving producer‑consumer ordering across an unordered interface, filed 2001‑08‑27 (§102(b) as pub.; §102(e) as patent). Same named inventor as the patent at issue. Discloses preserving producer‑consumer ordering across an unordered interface — i.e., the "route unordered, deliver ordering intact" idea in the patent's own closing paragraph. Relevant to claims 4, 9, 10. Gap: no incoming‑transaction queue/by‑type VN separation.

(17) US 2003/0188072 A1 — Creta (Intel), Peer‑to‑peer bus segment bridging, filed 2002‑03‑28 (§102(a) + §102(e)). Directly on the patent's peer‑to‑peer bridging premise. Relevant background/§103 art for independent claims' "incoming transactions… sent by a peer device" context. Gap: bridging, not VN separation.

(11) US 2002/0147869 A1 — Owen et al., Increasing bandwidth for issuing ordered transactions into a distributed communication system, filed 2001‑04‑04 (§102(b)). Ordered‑into‑unordered issuance. Relevant to claims 4, 9. Gap: no channel separation by type.

(18)/(19) US 2004/0019714 A1 / US 6,760,793 B2 — Kelley et al., Transaction credit control for serial I/O systems, filed 2002‑07‑29 (§102(a) pub.; §102(e) patent). Per‑transaction credit accounting. Closest cited art to claims 6 and 7 (separate credits; independent flow control) taken in isolation. Gap: credit control, not channelized traffic separation.

(1) EP 0 674 272 A1 — Hewlett‑Packard, Queue‑based predictive flow control mechanism, published 1995‑09‑27 (§102(b)). Predictive, queue‑occupancy‑based flow control. Most relevant cited art to claim 23 ("forwarding… based on a level of the first input queue") in isolation. Gap: telecom/network flow control; no bus agent, no VNs.

(2) US 6,148,001 A — Nokia, ATM multiplexing onto a virtual channel connection, filed 1997‑06‑12, issued 2000‑11‑14 (§102(b)). Discloses multiplexing packet streams onto virtual channels — marginally probative of claim 5 ("using a multiplexer… to separate the incoming transactions"). Gap: ATM/telecom; neither "agent of a coherent system" nor by‑type VN separation.

(21) US 2005/0141434 A1 — Cornett (Intel), Method, system, and program for managing buffers, filed 2003‑12‑24 (§102(e) only). Buffer/queue management generally; relevant to the queue architecture of claims 1(B)/14. Gap: no VN/channel separation by type.

(20) US 6,874,042 B2 — Dell, filed 2003‑03‑11 (§102(e)). Switch routing of peripheral/graphics data on an interconnect. Peripheral. Gap: no two‑queue VN architecture.

Tier 3 — Cited but with limited or no probative value

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4. Bottom-line answer on anticipation

No cited reference anticipates any claim of U.S. 7,165,131. The reason is structural, not a matter of degree:

• Claim 1 (and its twins 11, 14, 18) requires the conjunction of (i) a first input queue, (ii) forwarding at least some transactions to a second input queue, and (iii) by‑type separation into virtual networks of ≥3 channels and ≥2/≥3 channels.
• The cited art splits cleanly into two disjoint groups that never meet:
• Group A (virtual‑channel/virtual‑network art): WO 02/015470 / US 6,950,438; US 6,563,831; US 2003/0041185 / US 6,801,976. These teach by‑type or by‑need VC/VN separation with independent resources — but no two‑queue overflow structure and no multiplexer at queue outputs.
• Group B (queue/deadlock‑avoidance art): US 6,243,781; EP 0 674 272; US 6,912,612; US 7,047,374; US 2005/0141434. These teach queue overflow/set‑aside and arbitration — but no virtual channels or virtual networks.
• Because anticipation is single‑reference and element‑complete, and because every dependent claim inherits claim 1's elements, the dependent claims likewise cannot be anticipated — even where a reference (e.g., US 6,950,438 for claims 6–7, or EP 0 674 272 for claim 23) discloses the dependent claim's added limitation in isolation.

The citations are therefore best characterized as §103 obviousness art, not §102 anticipation art. The strongest combination a challenger would run: WO 02/015470 A2 / US 6,950,438 (primary — separate VCs by request type with independent buffers/credits over a noncoherent I/O fabric to avoid PCI‑type deadlock) in view of US 6,243,781 (secondary — first pipe overflowed to an auxiliary buffer under arbiter control) and, for claims 22–24, EP 0 674 272 (queue‑level‑based forwarding).

Claims‑at‑risk map (for §102 argument framing only)

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5. Art outside the citation record that is at least as material

Two items are cited in the patent's own background and are themselves §102(b) printed publications — the patent's admission of them is an evidentiary point in its own right:

• PCI Express Base Specification, Rev. 1.0 (published 2002‑07‑22) — cited at column 1; discloses traffic classes, virtual channels, and credit‑based flow control, i.e., much of the "virtual channel" substrate claim 1 presupposes.
• PCI Specification, Rev. 2.1 (published 1995‑06‑01) — cited for the posted/non‑posted ordering and "retry" forward‑progress rules the patent identifies as its problem.
• Also cited: USB Specification Rev. 2.0 (December 2000).

A complete invalidity analysis should treat these as §102(b) prior art and, per §102(b), their disclosures are imputed to the applicant. I did not independently retrieve their full texts within the search budget, so I am flagging this as a lead rather than a verified finding.

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6. Confidence, caveats, and residuals

High confidence: the identity of the patent (7,165,131, not the JP/TM collisions); the citation list and dates (from the authoritative full text, corroborated by Google Patents/Justia/FreePatentsOnline/uspto.report); the §102 subsection categorization (computed arithmetically from filing/issue/publication dates); the determination that US 2006/0101179 A1 (filed 2004‑10‑28) and the two 2004‑04‑27 sibling applications are not §102 prior art; the observation that WO 02/015470 A2's U.S. counterpart is US 6,950,438 B1 (Owen/Hummel/Keller, AMD/Alpha, issued 2005‑09‑27); and the observation that US 2005/0251611 A1 and serial 10/832,607 are the same document.

Moderate confidence: the substantive characterization of individual references. I retrieved and read substantial text on US 6,563,831, US 6,243,781, US 6,912,612, US 6,950,438/WO 02/015470, US 2003/0041185, and US 2003/0188072. For EP 0 674 272 A1, US 6,078,130 A, US 6,148,001 A, US 6,272,563 B1, US 6,516,375 B1, US 2002/0083256 A1, US 2002/0103948 A1, US 2002/0147869 A1, US 6,681,292 B2, US 6,874,042 B2, US 7,047,374 B2, US 2005/0141434 A1, US 2006/0101179 A1, US 10/832,606 and US 10/832,607, I relied on the patent's own citation table plus titles/assignees/abstract‑level knowledge — I did not retrieve full text for each, and my "brief description" for those is title‑ and abstract‑derived.

Explicit non‑answers / open items:

1. I could not query USPTO PatentCenter/PAIR directly (search budget exhausted); the bibliographic and legal‑status data rest on the authoritative full text supplied plus third‑party mirrors. A certified PatentCenter/assignment‑record check would be needed for legal certainty.
2. I did not independently verify the effective §102(e) U.S. filing dates for entries where the citation table shows only a publication date (notably the non‑provisional filing dates underlying US 6,912,612 and US 7,047,374, both tied to a 2002‑02‑25 provisional). Provisional‑date benefit under pre‑AIA §102(e) has its own requirements, so those two entries' prior‑art status could shift by up to a year.
3. The claim 1 vs. claims 14/18 inconsistency about whether the second virtual network has "a fourth channel and a fifth channel" (two channels) or "at least three other channels" is unresolved on the face of the document; it materially affects element (D) and a court would have to construe it. I flag it rather than pick a reading.
4. Claims 22–26 read as later‑added/amended claims (internal cross‑reference oddities: claim 22 restating "the method of claim 1," claim 26 depending from claim 4 but reciting routing language already in claim 2). Their effective priority and the prosecution‑history estoppel attaching to them cannot be assessed from the published text alone — the file wrapper would be required.
5. The PTAB hits my searches returned (petition artifacts referencing non‑patent PTACTS documents, and examiner search strings) concern unrelated subject matter (messaging channels; AMD Opteron architectural history) and are not proceedings on U.S. 7,165,131. Consistent with the prior litigation section, I found no §102‑creating or litigation event for this patent.

I'll ground this § 103 analysis against the cited prior art by verifying what the key references actually disclose.

Let me verify the remaining key references — the bypass-channel and credit-control art.

Obviousness Analysis — U.S. Patent No. 7,165,131 B2

Under 35 U.S.C. § 103(a) (pre‑AIA)

Scope note / proviso. This analysis builds on the two prior sections (bibliographic + litigation null result) and does not repeat them. It draws on the Prior Art section of the US7165131 Google Patents page (the 23 "Patent Citations," 2 "Non‑Patent Citations," and their metadata) as the reference universe, supplemented by targeted verification of the primary references' actual disclosures and publication dates. Critically: for most of the 23 cited references I retrieved titles, dates, assignees, abstracts, and selected passages only — not full‑text, column/line‑verified disclosures. Element mappings below are therefore stated as "appears to disclose" and identify the verification still required. Where I rely on a reference outside the page's citation list, I flag it explicitly.

One correction of record, from diligence on the citation list: US 2006/0101179 A1 (Lee, "Starvation prevention scheme for a fixed priority PCI‑Express arbiter…", published 2006‑05‑11, priority 2004‑10‑28) was published after, and filed after, the '131 priority date of 2004‑04‑27. It is therefore not § 102 or § 102(e) prior art and should be excluded from any § 103 combination. (It appears on the page among "Citations" but cannot be used.)

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1. Governing legal framework

The '131 has a priority/filing date of 2004‑04‑27, so pre‑AIA § 103(a) governs. The controlling test is Graham v. John Deere Co., 383 U.S. 1 (1966) (scope/content of art; differences; level of ordinary skill; secondary considerations), as refined by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007):

• A combination of familiar elements according to known methods is obvious when it "does no more than yield predictable results" (KSR, 550 U.S. at 416).
• "If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill." Id. at 417.
• Motivation may come from the references themselves, the knowledge/skill of the artisan, or the nature of the problem to be solved. MPEP § 2143, rationales (A)–(G).

A threshold point counsel must handle up front: several of the strongest references are Intel references. Under pre‑AIA § 103(c), commonly owned § 102(e)/(f)/(g) art cannot be used in a § 103 rejection. I confirmed each key Intel reference qualifies under § 102(a) or § 102(b) (published before 2004‑04‑27), so § 103(c) does not shelter them — see the date table in § 4.

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2. Level of ordinary skill in the art

Bachelor's degree in electrical engineering or computer science plus 2–4 years of experience in computer system architecture and I/O interconnect design, or a master's degree plus ~1–2 years. The artisan would be familiar with: the PCI/PCI‑X/PCI Express ordering model (posted vs. non‑posted vs. completion); the Producer–Consumer ordering model; split‑transaction read completions; credit‑based flow control; and — importantly — the parallel‑computing literature on virtual channels and virtual networks used for deadlock avoidance in interconnection networks. That last point matters, because the '131's own description treats "virtual network" as a known abstraction (a group of virtual channels encompassing all message classes, with independent buffering and flow control).

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3. Claim structure and construction notes

Four independent claims: 1 (method), 11 (article/machine‑accessible medium), 14 (apparatus), 18 (system). Consistent with the prior section's flag, the independents are internally inconsistent on the second virtual network:

Claim 14's and 18's "or" is a disjunctive scope that, read broadly, requires only one of the two virtual networks to have the recited channel count. That disjunction materially weakens these claims against the art (see § 12). For § 103 purposes I analyze the narrowest reasonable reading (both networks present, first VN ≥ 3 channels, second VN ≥ 2 channels).

Under the specification, "virtual network" = a group of virtual channels including all message classes, each VN having independent buffering and flow control. So the claim core is: two segregated traffic classes of channels/VNs, with a two‑queue intake stage that selectively overflows from one queue to a second.

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4. Prior‑art reference table (with pre‑AIA dispositions)

Supplementary (not on the cited list, same AMD family and therefore reasonably combinable): US 6,721,816 B1 (AMD, "Selecting independently of tag values…") discloses an I/O node supporting three virtual channels: Non‑Posted, Posted, and Response, with separate per‑VC buffers, tagging logic, and a Pass Posted Write (PPW) bit — a three‑channel segregation by transaction class. (US6721816)

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5. Ground A — AMD '470 in view of Intel '781 (and Avici '831)

Proposed rejection: claims 1, 2, 4, 8, 11, 16, 17, 18, 19, 20, 26.

Claims 2, 4, 8, 26 fall out of AMD '470 directly (posted writes vs. non‑posted reads; "separate resources are allocated to the virtual channels"). Claim 16 is met by AMD '470's claim 7 (third node with per‑VC packet buffers). Claims 18–20 are met by AMD '470's packet‑based bidirectional (point‑to‑point) links and its coherent fabric. Claims 17/19 ("peer device having a non‑coherent protocol") map to AMD '470's noncoherent link/fabric. Claim 11 adds only a machine‑accessible medium — the '131 specification itself states the logic "may include code or logic," so In re Beauregard‑style medium claims rise or fall with the method.

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6. Ground B — Ground A further in view of Creta '976 (US 6,801,976)

Proposed rejection: claims 3, 5, 9, 10, 14, 15, 21, 24, 25.

• Claim 5 & 14 (multiplexer coupled to outputs of first and second queues, feeding a transaction/protocol layer): Creta '976 discloses an "inbound multiplexer 180" that "receives data and signals … from the IOQ 120 and the IOQ RBB 125" and forwards to the unordered protocol (the coherent interface). That is, element for element, a multiplexer coupled to the outputs of a first queue and a second (bypass) queue providing a selected output to a protocol/transaction layer. This is a near‑perfect read of claims 5/14 and is the single strongest reference mapping in the whole analysis.
• Claims 9 & 10 (completion packet from completer to requester, on a different channel): Creta '976's OOQ issues "a write completion for a posted write" and stores "completions of the inbound transactions"; AMD '470 provides a dedicated "Responses" virtual channel. Motivation: PCI split‑transaction completions must be separable from requests to preserve Producer–Consumer ordering.
• Claim 3 / 15 / 21 (standard, bypass, completion channels): Combining AMD '470's three VCs (posted / non‑posted / response) with Intel '612's bypass bus and "virtual channel qualifier" and Creta '976's bypass buffers yields the claimed trio. The '131's own labels ("non‑coherent standard," "non‑coherent bypass," "completion") are functional descriptors; the functions (normal traffic, bypass traffic, completions) are disclosed.
• Claim 24 (forwarding posted transactions to the second queue): Creta '976 pushes reads to the bypass buffer "to permit the posted writes … to progress" — i.e., a bypass queue whose purpose is posted‑write progress. Selecting which class is moved aside is a predictable design choice with an articulated benefit (avoid head‑of‑line blocking), satisfying KSR's "predictable variation" rationale.
• Claim 25 (receive on VN1, transmit on VN2): Creta '976's ordered‑domain → multiplexer → unordered‑protocol path, and outbound demultiplexer → ordered domain, is a receive‑on‑one‑domain / transmit‑on‑another architecture.

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7. Ground C — Ground B further in view of US 6,760,793 and Avici '831

Proposed rejection: claims 6, 7, 12, 13.

• Claim 6 / 12 ("separate credits between first and second transaction types"): AMD '470 ("separate resources are allocated to the virtual channels"); Avici '831 ("a credit field that indicates an amount of buffer space available in a downstream router," and per‑channel credit events); and directly on point, US 6,760,793 ("Transaction credit control for serial I/O systems"). Motivation: independent credit pools are the recognized mechanism for preventing one traffic class from consuming another's buffering — a well‑understood solution to the problem both AMD '470 and the '131 recite.
• Claim 7 / 13 ("independently controlling flow of the first and second transaction types"): Avici '831's express teaching that "congestion in one virtual network is substantially nonblocking to data flow through other virtual networks," plus per‑VC flow control.

This ground is strong: the claimed credit separation is the stated purpose of virtual‑channel segregation in the interconnection‑network art.

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8. Ground D — Claim 23 (forwarding based on a level of the first input queue)

Ground B further in view of EP 0 674 272 A1 (HP, "Queue‑based predictive flow control mechanism," pub. 1995).

Intel '781 forwards a transaction based on a retry/rejection, not queue occupancy. The '131 specification itself frames the mechanism in terms of the queue being "backed up." EP '272 supplies flow control keyed to queue occupancy levels, and AMD '470 supplies buffer‑availability‑based transmission decisions. Motivation to combine: predictive/high‑water‑mark overflow control to prevent queue overflow and head‑of‑line blocking — a textbook application. Claim 23 is likely obvious over this combination, though it is the element most dependent on general artisan knowledge rather than an express teaching.

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9. Ground E — Claims 22 and 25 (virtual‑network transition / traversal)

Claim 22: "routing a transaction from the agent via the first virtual network to a second agent; and routing the transaction from the second agent via the second virtual network." The '131 specification supports this via the VNA ↔ VN0/VN1 transition described at the link layer (a blocked message transitions to VN0 or VN1 and back to VNA at a subsequent link).

Prior art: Avici's family (including US 6,563,831 and the later source‑based/egress‑based virtual‑network art, e.g., Avici's "Gamma graph" patents) discloses traversing a source‑based virtual network and then an egress‑based virtual network to prevent tree saturation and deadlock — structurally the same "enter on one VN, leave on another" concept. AMD '470 and Creta '976 both describe packets traversing intermediate nodes and crossing domain boundaries.

Caveat: This is the weakest of the grounds. The claim's "second agent" transition is not a literal disclosure in the cited references, and the rejection would rest on combining the '131's own VNA description with the general VN‑transition art. A challenger should expect argument here; a patentee would argue that the specific re‑classification at a receiver is not taught.

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10. Consolidated motivation to combine

The motivation is unusually easy to establish here because the '131 specification concedes the problem, and the references independently recite the same problem:

1. Same field, same problem (MPEP 2143(A), (C)). The '131 Background states: "a need exists to provide for deadlock‑free transfer of transactions through a system, where multiple protocols exist for different components of the system," and notes that PCI's retry mechanism is unavailable where credit tracking occurs at different layers. AMD '470's background says the same thing about PCI posted‑write ordering across coherent/noncoherent fabrics and deadlock‑free operation. Intel '781's background diagnoses the posted‑write/non‑posted‑read deadlock in an outbound pipe and criticizes the retry approach as performance‑limiting. Intel '976 addresses ordering across an unordered (coherent) interface. When the references articulate the same problem the patent articulates, motivation is established.

2. Known technique applied to a known device ready for improvement (MPEP 2143(C)). Virtual channels + virtual networks for deadlock‑free routing were a mature technique in the interconnection‑network art (Avici '831, and the ATM/parallel‑computing literature the patent itself cites: ATM virtual channel connections in US 6,148,001, and Avici's fabric). AMD '470 had already transferred that technique into the multiprocessor I/O fabric context. Applying it to an I/O hub bridging a PCI/PCI‑Express domain to a point‑to‑point coherent fabric is "the application of a known technique to a known device ready for improvement to yield a predictable result." KSR, 550 U.S. at 417.

3. Combining prior art elements according to known methods (MPEP 2143(A)). Intel '781's auxiliary buffer (first→second queue forwarding) and AMD '470 / Creta '976's per‑class segregation are each independently known; placing a known bypass/overflow queue upstream of a known per‑class VC segregator yields no more than the sum of the parts.

4. Industry design incentive / market forces (MPEP 2143(F)). The PCI Express transition to point‑to‑point (the '131 cites the PCI Express Base Spec, Rev. 1.0, 2002‑07‑22) and the contemporaneous Intel CSI program (evidenced by the three same‑day Intel filings: 10/832,606, 10/832,607, and the '131 itself) created strong demand for deadlock‑free peer‑to‑peer transfer across a coherent fabric.

5. Obvious to try (MPEP 2143(E)). The number of channels/VNs is small and bounded (2, 3, or 4), and the '131's own Table 1 mapping is a design choice it expressly disclaims as limiting ("transactions … may be transmitted on any desired virtual channel").

6. Simple substitution (MPEP 2143(B)). Substituting a per‑class virtual/bypass channel for the physical bypass bus of Intel '612 is an available design option with a known benefit.

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11. Claim‑by‑claim quick reference

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12. Where the § 103 case is vulnerable (anticipated rebuttals)

A challenger must anticipate these counterarguments:

1. The word "virtual network." All the cited coherent‑fabric references (AMD '470, Intel '781, Creta '976) speak in terms of virtual channels, not virtual networks. Avici '831 supplies the VN terminology but is internet‑router art. A patentee will argue non‑analogous art under In re Bigio/In re Clay and that the VN grouping is the point of novelty. Rebuttal: the '131 specification itself defines a virtual network as merely "a group of virtual channels that includes all the message classes" — so the claim's "virtual network" adds little beyond a grouping feature that AMD '470 arguably performs (four VCs, each with separately allocated resources). In re ICON Health & Fitness (analogous art measured by field of endeavor and problem to be solved) supports admissibility.

2. The claim‑1 vs. claims‑14/18 channel‑count inconsistency. Claim 1 requires the second VN to have exactly "a fourth channel and a fifth channel," while claims 14/18 require "at least three other channels." A challenger applying AMD '470's four VCs to claim 1 must show a two‑channel second network; AMD '470's probes VC gives a fourth, but a fifth is not clearly disclosed. Either (a) argue claim 1's "including" is non‑exhaustive (open‑ended), or (b) rely on a reference with exactly two additional channels. Conversely, claims 14/18's disjunctive "or" limits the exposure.

3. Claim 14/18 disjunction. Because those claims recite "at least three channels or … at least three other channels," a single three‑channel reference (AMD '470, or US 6,721,816's Non‑Posteded/Posted/Response trio) may satisfy them even without a second VN — a construction the patentee will fight but which materially broadens the art's reach.

4. § 103(c) bars use of any of the cited art that qualifies only as § 102(e)/(f)/(g). I verified the key Intel references all publish before 2004‑04‑27, so they are § 102(a) or § 102(b) art and are not sheltered. But if a challenger relies on any reference solely via its § 102(e) filing date, the common‑ownership argument revives.

5. Same‑inventor art. Creta '976 and its publication US 2003/0041185 are § 102(b) art (published 2003‑02‑27, more than one year pre‑filing) notwithstanding that Creta is a named inventor on both. That is legally correct but invites a "this is just the inventor's own earlier work" narrative — which, if anything, helps the obviousness case (an incremental improvement over the inventors' own prior system) but should be framed carefully.

6. Examiner allowance. The '131 issued with 26 claims, and claim 22–26 read as later‑added amendments (as the prior section flagged). The prosecution history thus warrants review for any statements distinguishing the prior art, which could create prosecution history estoppel or, worse, a narrowing amendment I have not seen.

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13. Secondary considerations

There is no evidence in the record of nexus‑bearing secondary indicia — no unexpected results, long‑felt but unmet need, industry praise, copying, licensing program, or commercial success attributable to the claimed subject matter. Two facts bear on the weight of any such argument:

• The patent lapsed for non‑payment of maintenance fees effective 2019‑01‑16 (8‑year fee paid 2014‑06‑18; no 12‑year fee), and the entire foreign family (EP 1591908A1 ceased; KR 100715741B1 expired; CN 100524271C expired; TW I264904B right cessation) went abandoned. Asserting commercial success on an abandoned patent is difficult.
• Per the prior section, there is no known litigation involving the '131 — consistent with an incremental, promptly‑abandoned implementational improvement rather than a foundational invention. Diligence in the litigation section should be re‑verified before any of this is relied upon; it is a good‑faith null result, not a certified negative.

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14. Bottom line

The '131's claims are, on this preliminary record, vulnerable to a § 103(a) rejection over a small number of well‑dated references:

• Primary ground (broadest): AMD WO 2002/015470 A2 (US 6,950,438) in view of Intel US 6,243,781 B1 — AMD supplies transaction‑type separation into plural virtual channels with separate resources across coherent/noncoherent fabrics for expressly deadlock‑free operation; Intel '781 supplies the first‑queue → second‑queue (auxiliary buffer) forwarding. Adding Avici US 6,563,831 supplies the "virtual network" grouping and independent, non‑blocking per‑VN flow control.
• Secondary ground (kills the dependent claims): above in view of Intel US 6,801,976 (Creta) — whose inbound multiplexer over an ordering queue and a read‑bypass buffer maps almost element‑for‑element onto claims 5/14, and whose posted‑write completions and bypass buffers map onto claims 9/10 and 3/15/21 — plus US 6,760,793 / Avici '831 for the separate‑credit and independent‑flow‑control claims (6, 7, 12, 13), and EP 0 674 272 for the queue‑level forwarding claim 23.
• Weakest link: claims 22 and 25 (virtual‑network transition between agents), which rest on combining the '131's own VNA discussion with the general VN‑transition art rather than on an express disclosure.

Motivation is well supported because the '131 and the references recite the same problem (deadlock‑free transfer between a PCI‑style ordered domain and a point‑to‑point coherent fabric, without PCI's retry), and because separate virtual channels with independent credits were the recognized solution to that problem.

Required before relying on this analysis: (i) full‑text, column/line verification of every "appears to disclose" mapping above — I worked from abstracts, metadata, and selected passages, not complete specifications; (ii) the '131's prosecution history (IDS contents, any amendments and arguments, particularly for claims 22–26); (iii) confirmation of the § 102(e) provisional‑support chain for US 6,912,612; and (iv) re‑verification of the no‑litigation null result.