Obviousness

Obviousness Analysis of US Patent 7007259 Under 35 U.S.C. § 103

This analysis assesses the obviousness of claims in US Patent 7007259 (hereinafter '259 patent) by identifying combinations of prior art references that would render the claimed invention obvious to a person having ordinary skill in the art (PHOSITA) at the time of the invention (priority date July 31, 2003).

The '259 patent addresses the problem of inserting dummy metal for chemical-mechanical planarization (CMP) while minimizing negative timing impact, particularly on critical clock nets. The invention proposes prioritizing dummy regions so that those adjacent to clock nets are filled last, and further prioritizing those adjacent to wider clock nets to be filled even later.

The background of the '259 patent explicitly states that minimizing timing impact from dummy metal, especially on clock nets, was a known problem, and that "the dummy fill tool is programmed to maintain a larger distance between wires of clock nets and the inserted dummy metal." The patent describes this traditional approach as "simplistic" and highlights its disadvantages, such as requiring multiple runs to meet density requirements. This establishes that the problem of timing impact from dummy fill, and the particular importance of clock nets, was well-recognized in the prior art.

Claim 1: Method for Inserting Dummy Metal

Claim 1: A method for inserting dummy metal into a circuit design, the circuit design including a plurality of objects and clock nets, the method comprising:
(a) identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions; and
(b) prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last, thereby minimizing any timing impact on the clock nets.

Combination of Prior Art References: US20030204832A1 (Nec) in view of US6751785B1 (Ubitech) and general knowledge of a PHOSITA regarding clock net criticality.

• US20030204832A1 (Nec): This reference discloses an "Automatic generation method of dummy patterns." It teaches "calculating the area ratio of actual patterns in each unit area," "detecting dummy pattern regions," and "generating dummy patterns in the dummy pattern regions." These disclosures collectively satisfy element (a) of Claim 1, which involves identifying free spaces suitable for dummy metal insertion as dummy regions. Nec's stated objective to "prevent degradation of circuit characteristics by the generated dummy patterns" also broadly aligns with minimizing negative impact.

• US6751785B1 (Ubitech): This patent directly addresses "limiting increase in capacitance due to dummy metal fills utilized for improving planar profile uniformity." It describes "defining a region of interest around the active circuit components" and "inserting dummy metal fills only if an increase in parasitic capacitance of the active circuit components is within a predetermined limit." Ubitech explicitly teaches minimizing parasitic capacitance from dummy metal to active circuits, which directly relates to minimizing timing impact (element (b) of Claim 1).

• Motivation for Combination: A PHOSITA, seeking to improve dummy fill methods to effectively minimize timing impact (as described in Ubitech for active components generally), would be motivated to adapt a general dummy pattern generation method (like Nec's) to be "clock-net aware." It was well-known in the art (and acknowledged in the '259 patent's background) that clock nets are of critical importance and require care to minimize negative timing impact. Given Ubitech's teaching of limiting capacitance increase around active circuit components, and the common general knowledge that clock nets are particularly critical active components, it would have been obvious to a PHOSITA to treat dummy regions adjacent to clock nets differently. Specifically, to implement Ubitech's principle of limiting capacitance increase for clock nets, a PHOSITA would be motivated to prioritize these clock-adjacent dummy regions to be filled last, thereby maximizing the distance between dummy metal and clock nets and minimizing timing impact, as required by element (b). This combination addresses the known problem of timing degradation due to dummy metal near critical signals, particularly clock nets, using established dummy fill techniques and known methods for managing parasitic effects.

Claim 18: Computer-Readable Medium

Claim 18: A computer-readable medium containing program instructions for inserting dummy metal into a circuit design, the circuit design including a plurality of objects and clock nets, the program instructions for:
(a) identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions; and
(b) prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last, thereby minimizing any timing impact on the clock nets.

Obviousness: Claim 18 is a method claim directed to a computer-readable medium with program instructions for performing the same steps as Claim 1. If the method of Claim 1 is obvious, then implementing that method as computer program instructions on a computer-readable medium would also be obvious to a PHOSITA skilled in software development for electronic design automation (EDA) tools. The conversion of a known process into computer-executable instructions is a routine engineering task.

Claim 35: Method for Inserting Dummy Metal with Timing Factors

Claim 35: A method for inserting dummy metal into a circuit design, the circuit design including a plurality of objects and clock nets, the method comprising:
(a) identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions;
(b) determining which of the dummy regions are located adjacent to clock nets;
(c) assigning a timing factor to each dummy region based on an width of an adjacent clock net wire;
(d) sorting the dummy regions based on the timing factors; and
(e) inserting dummy metal into the sorted dummy regions such that the dummy regions located adjacent to increasingly wider clock nets are filled last, thereby minimizing any timing impact on the clock nets.

Combination of Prior Art References: US20030204832A1 (Nec) in view of US6751785B1 (Ubitech), US20030177464A1 (Fujitsu '177), and general knowledge of a PHOSITA regarding clock net hierarchy and criticality.

• US20030204832A1 (Nec): As discussed for Claim 1, Nec discloses identifying dummy regions (element (a)).

• US6751785B1 (Ubitech): As discussed for Claim 1, Ubitech provides the motivation and teaching for minimizing capacitance/timing impact near critical active circuits (element (e) – minimizing timing impact, and motivation for prioritization).

• US20030177464A1 (Fujitsu '177): This patent describes an "Integrated circuit layout method and program thereof permitting wire delay adjustment." While not explicitly about dummy metal, it highlights the importance of fine-tuning timing characteristics of wires in IC layout. This reinforces the PHOSITA's motivation to consider wire characteristics when dealing with timing-sensitive aspects.

• PHOSITA Knowledge: The '259 patent's own detailed description explicitly states, "In a clock tree, the width of a wire is indicative of its order in a hierarchy. A wide wire is likely to be supplying current to more branches than a thinner wire, and is therefore more timing critical." This statement reflects common general knowledge in the field of IC design. Therefore, determining criticality based on wire width for clock nets, and consequently assigning a "timing factor" based on the width of an adjacent clock net wire (element (c)), would have been obvious to a PHOSITA. Once such factors are assigned, sorting the dummy regions based on these factors (element (d)) is a straightforward and conventional data processing step to enable filling them in a desired order (element (e)).

• Motivation for Combination: Starting from Nec's general dummy fill method and Ubitech's teaching to limit capacitance around active components to minimize timing impact, a PHOSITA would naturally seek to apply this with greater specificity to the highly timing-critical clock nets. Given the universally understood principle that wider clock net wires are generally more timing critical, a PHOSITA would be motivated to differentiate between dummy regions adjacent to clock nets of varying widths (elements (b) and (c)). To effectively implement a refined "limiting increase in capacitance" strategy (Ubitech) or "wire delay adjustment" (Fujitsu '177) that accounts for varying clock net criticality, assigning a quantitative "timing factor" based on wire width is a logical and obvious step. Subsequently, sorting the dummy regions based on these timing factors (element (d)) to ensure that regions adjacent to increasingly wider (and thus more critical) clock nets are filled last (element (e)) would be a straightforward engineering decision to optimize timing predictability and minimize iterative design cycles, as the '259 patent itself identifies as a problem with traditional methods.