Obviousness

Obviousness Analysis of U.S. Patent 6,813,742 under 35 U.S.C. § 103

This analysis evaluates the obviousness of the independent claims of U.S. Patent 6,813,742 ('742 patent) in light of the prior art cited during its prosecution. The standard for obviousness under 35 U.S.C. § 103 is whether the claimed invention as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (a "POSA"). This analysis focuses on whether a POSA would have been motivated to combine the teachings of the existing prior art to arrive at the invention claimed in the '742 patent.

The core of the '742 patent, as defined in independent claims 1 and 6, is a turbo decoder architecture for 3G wireless systems that uses at least two soft-in/soft-out (SISO) decoders in a serially-coupled, circular, and iterative configuration. The key features are the iterative feedback loop and the use of MAP (or Log-MAP) algorithms to process soft decision information.

A person of ordinary skill in the art at the time of the invention (priority date of January 2, 2001) would have been an electrical engineer or computer scientist with experience in digital communications, error-correction coding, and integrated circuit design, particularly with knowledge of algorithms like Viterbi and MAP, and familiarity with emerging 3G wireless standards.

Combination of Prior Art Rendering Claims Obvious

The claims of the '742 patent would have been obvious to a POSA by combining the foundational teachings of U.S. Patent 5,446,747 ('747 patent) with the practical implementation details disclosed in U.S. Patent 6,526,539 B1 ('539 patent).

• '747 Patent (Berrou et al.): This patent is a foundational reference for turbo codes and explicitly teaches the core concept of iterative decoding. It discloses a decoder comprising at least two constituent decoders connected in a feedback loop. Crucially, it describes the process where one decoder calculates and outputs "extrinsic information" (a form of soft decision) which is then used as an input by the subsequent decoder. This iterative process, passing refined probabilistic information back and forth, is the central mechanism of turbo decoding and directly maps to the "iteratively processing," "circular circuit," and feedback loop elements recited in claims 1 and 6 of the '742 patent.

• '539 Patent (Fujitsu): This patent, filed in June 1999, addresses the practical hardware implementation of a turbo decoder. It explicitly discloses a turbo decoder architecture with two MAP decoders, an interleaver, and a de-interleaver. The components are arranged for iterative decoding, where the output of one decoder is passed through memory (the interleaver/de-interleaver) to the other. This patent provides a clear and concrete hardware blueprint for the system conceptually introduced by the '747 patent.

Motivation to Combine

A person of ordinary skill in the art in early 2001 would have been strongly motivated to combine the teachings of the '747 and '539 patents for the following reasons:

1. Solving a Known Problem with a Known Solution: The '747 patent established the theoretical and functional basis for turbo codes, demonstrating their superior performance. The primary challenge then shifted to creating efficient, high-speed hardware implementations suitable for commercial applications like the emerging 3G wireless standards. The '539 patent directly addresses this challenge by providing a specific, practical architecture for a hardware-based turbo decoder. A POSA, tasked with designing a high-performance decoder for a 3G baseband processor, would have naturally looked to the foundational principles of the '747 patent and sought out known methods for efficient hardware implementation, such as those described in the '539 patent.

2. Predictable Results: Combining the iterative decoding method from the '747 patent with the hardware architecture from the '539 patent would yield a result that was entirely predictable: a functional, hardware-based turbo decoder. The '539 patent is essentially an implementation of the concepts taught in the '747 patent. The combination does not produce an unexpected or surprising result; rather, it achieves the exact goal for which both technologies were developed—efficient, high-performance error correction.

3. Use of Log-MAP as a Known Optimization: The '742 patent claims the use of a "logarithm approximation algorithm," referring to the Log-MAP algorithm. The standard MAP algorithm, while optimal, was known to be computationally intensive due to its many multiplication operations. The Log-MAP algorithm, which operates in the log domain and replaces multiplications with simpler additions, was a well-known and widely adopted simplification by 2001. A POSA would have considered the use of Log-MAP not as an inventive step, but as a standard and obvious design choice for implementing a MAP-based decoder in an application-specific integrated circuit (ASIC) to reduce complexity, cost, and power consumption, all of which are critical for 3G devices. The '742 patent itself touts this as an advantage, but it was a common practice in the field.

Conclusion on Obviousness

• Claim 1 recites a baseband processor with at least two serially coupled soft decision decoders in a circular circuit, with memory modules to facilitate feedback. The '747 patent teaches the circular, iterative processing, and the '539 patent provides a concrete example of this architecture using two MAP decoders and memory (interleaver/de-interleaver). A POSA would have found it obvious to implement the iterative method of '747 using the hardware structure of '539.

• Claim 6 recites a method of iterative decoding using a MAP (or logarithm approximation) algorithm, generating and storing soft decisions, and feeding the output of the last decoder back to the first. This is the fundamental process of turbo decoding as taught by the '747 patent. The '539 patent describes this same method in the context of a specific hardware implementation. The selection of a Log-MAP algorithm would have been an obvious and routine optimization for any skilled engineer implementing such a decoder in hardware.

Therefore, the combination of the foundational iterative decoding method disclosed in the '747 patent with the practical hardware architecture shown in the '539 patent would have rendered the independent claims of the '742 patent obvious to a person of ordinary skill in the art at the time of the invention. The '742 patent claims a predictable combination of known elements from the prior art that were established solutions to well-understood problems in the field of digital communications.