US 6625694

I'll verify the patent against live sources and check for any 2026 CAFC docket activity.

Verification complete. Here is the summary.

US Patent 6,625,694 (US 6,625,694 B2) — Verified Summary

Important identifier note: The number as given, 6625694, is the correct, literal identifier for this patent (short form of US 6,625,694 B2). I did not auto-correct or alter it.

Abstract (as issued)

An algorithm for selecting a directory entry in a multiprocessor-node system. In response to a memory request from a processor in a processor node, the algorithm finds an available entry to store information about the requested memory line. If at least one entry is available, the algorithm uses one of the available entries. Otherwise, the algorithm searches for a "shared" entry. If at least one shared entry is available, it uses one of the shared entries. Otherwise, it searches for a "dirty" entry. If at least one dirty entry is available, it uses one of the dirty entries. In selecting an entry, the algorithm uses a "least-recently-used" (LRU) approach because an entry not recently used is more likely to be stale. Further, to improve system performance, the algorithm preferably uses a shared entry before using a dirty entry. In the preferred embodiment, the processor node includes at least one processor having a respective cache connected via a bus to main memory.

Independent claims — plain language

Claim 1 (system): A data processing system with (a) main memory, (b) multiple processors each with its own cache holding multiple cached lines, (c) a memory controller, and (d) a sparse directory that has fewer entries than the main memory has memory lines, used to track cache-line states. On a new request for a cache line, an algorithm uses those stored states to allocate a directory entry for the requested line; and if all directory entries represent memory lines in transitional (transient) states, the algorithm retries the request rather than evicting in-use entries.

Claim 16 (method): A method of selecting a directory entry from multiple entries that carry state information, comprising: receiving a request to select among the directory entries; using that state information to make the selection; and allowing a re-request if it is determined that all of the directory entries represent cached lines in transitional states.

(Claims 2–15 depend from claim 1; claims 17–24 depend from claim 16.) Notable dependents:

• Claim 2 — ranking a "shared" entry higher in allocation preference than a "dirty" entry.
• Claim 3 — among the highest equally ranked entries, allocate the least-recently-used one.
• Claim 7 / 22 — invalidating the cached line represented by the allocated/selected entry.
• Claim 9 — the directory entry associated with a transient state is not chosen.
• Claims 8 and 23 — there is only one type of dirty state.
• Claims 10 and 24 — shared states have a hierarchical level separate from other states.
• Claim 11 — entry format: state information field + per-processor bit-vector field + tag field identifying the main-memory segment.
• Claims 18–21 — the ordered hierarchy: invalid first, then shared (with LRU), then dirty (with LRU).

Underlying algorithm (from the specification, FIG. 7)

1. Look for an entry whose state is invalid (available) → allocate it.
2. Else look for a shared entry → pick the LRU shared entry, invalidate it, reuse it.
3. Else look for a dirty entry → pick the LRU dirty entry, flush it (invalidate and write the cached data back to memory), reuse it.
4. If neither shared nor dirty is found (i.e., all entries are in transient states), ask the processor to retry the request later.

The stated rationale: invalidating a shared entry only requires sending invalidations, whereas evicting a dirty entry requires a write-back to memory — so preferring shared over dirty reduces memory traffic; and LRU entries are more likely to be stale (a cache may have silently replaced a line without updating the directory).

Search results on litigation / CAFC 2026 dockets

• No CAFC 2026 docket activity for US 6,625,694 was found. My searches for "6625694 CAFC 2026 docket" returned unrelated 2026 Federal Circuit matters (e.g., tariff/IEEPA appeals and a Headwater Research appeal, USCA Case No. 26-1884, from E.D. Tex.), none of which reference this patent.
• One incidental hit: a USPTO PTAB/petition-style document (ptacts.uspto.gov, petition 1557466) contains the literal search string US-6625694- among its query logs. That document itself concerns a different application (Serial No. 12/121,531, Rozas, "Memory Management for Cache Consistency"); the 6625694 string appears only as a search term in a query table. I would not treat this as evidence of a challenge to US 6,625,694 without the actual petition text.
• The Google Patents record shows the patent as Expired – Lifetime, with fee payments at 4, 8, and 12 years and an anticipated expiration of 2019-05-03. Family size is small (US + JP).

Uncertainty / caveats

• The abstract, claims, dates, inventors, and assignee above are taken from the authoritative full text of US 6,625,694 B2 and are confirmed by the Google Patents and Justia records.
• I have not located any authoritative record of a 2026 CAFC appeal or district-court assertion involving this specific patent. If such a case exists, it did not surface in my searches; absence of results here is not proof of absence of litigation.
• Note a common-confusion hazard: 6625694 is also used as an unrelated FAERS case number in an FDA adverse-event report, and appears as a search string in a PTAB document — neither concerns this patent.

I'll research litigation involving US patent 6625694 specifically. Let me search multiple sources.

Let me search patent litigation databases more specifically.

Summary of Findings

I searched for litigation specifically involving US Patent No. 6,625,694 ("System and method for allocating a directory entry for use in multiprocessor-node data processing systems"; Fujitsu Limited; filed 1999‑05‑03; granted 2003‑09‑23; expired ~2019‑05‑03).

Result: I found no known litigation asserting or involving US 6,625,694. I could not identify any district court case, ITC investigation, CAFC appeal, or PTAB proceeding in which this patent was the patent‑in‑suit.

What the searches did return

Caveats (important)

• Tool limitation: I was cut off partway through querying litigation‑specific databases (Unified Patents litigation portal, CourtListener/RECAP, Docket Navigator). The site:portal.unifiedpatents.com 6625694 query returned zero results, but I cannot rule out that a case exists that was not surfaced.
• The absence of a Google Patents "Litigation" section is suggestive but not dispositive — that feature is often incomplete for older patents and for cases that were filed only in state court or settled early.
• I did not find any evidence of assertion, so I cannot provide plaintiff/defendant/jurisdiction/case‑number/filing‑date/outcome entries.

Bottom line

Based on the sources I was able to consult, no litigation involving US Patent 6,625,694 is known. The only third‑party proceeding reference I located treats the patent merely as cited prior art in an unrelated PTAB petition. If a definitive negative is required for a legal opinion, I recommend a paid search of Docket Navigator, Lex Machina, or PACER/RECAP under the exact number "6,625,694," plus a check of Fujitsu's assertion history — as my search coverage here was incomplete.

I do not want to fabricate case details, so I am explicitly reporting a negative result rather than inferring cases from the similarly numbered patents (e.g., 6,635,694 or 5,625,694) that appeared in unrelated results.

PTAB proceedings on US 6,625,694

Source of record: the structured "PTAB proceedings on file" block supplied in this prompt (USPTO Open Data Portal ingest), cross-checked against public web sources. No proceeding numbers are invented below.

Proceedings overview

Total AIA trial proceedings on file: 0. There are no IPRs, PGRs, or CBMs involving US 6,625,694 in the ODP structured data, and no active, instituted, settled, or denied AIA trial could be located through web search of PTAB/public docket sources. The breakdown of status is therefore: active — 0; claims invalidated — 0; claims sustained — 0; settled — 0; institution denied — 0. The bottom line for a defendant is not "the patent is hardened through surviving IPRs" but rather "this patent was never challenged at the PTAB and, per the structured data, its term is already over (anticipated expiration 2019-05-03) — the defensive leverage lies in the expired term and the pre-expiration damages window, not in an IPR record."

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No proceedings to report

I cannot write up even one ### {PROCEEDING_NUMBER} — {Petitioner} v. {Patent Owner} entry, because no AIA trial number exists to report. The structured block is the canonical list and it is empty for this patent; web search returned no IPR/PGR/CBM docket for U.S. Patent No. 6,625,694, no FWD, and no Federal Circuit appeal arising from a PTAB trial on it. I will not manufacture a number, panel, or FWD to fill this section.

One caveat, flagged but unverified. A web hit surfaced a PTAB petition exhibit (petition artifact on ptacts.uspto.gov, petition ID 1557466) that contains a prior-art/keyword search string including US-6625694. That is evidence that the '694 patent appeared in someone else's petition search log — presumably as a searched or cited document — not evidence that an AIA trial was filed or instituted on the '694 patent. I could not confirm the parent proceeding, the identity of the patent under review there, or whether the '694 cite is a substantive ground. Treat it as a research lead only; do not represent to a court or an adversary that an AIA proceeding exists on this patent.

Strategic summary

Claim status: all claims UNTESTED at the PTAB. Claims 1–17 and 18–24 (24 claims total, of which claims 1 and 16 are the independent claims) have never been construed or adjudicated in an AIA trial. There is no FWD cancelling or sustaining any claim, so no claim is "dead" by virtue of a PTAB record. Nothing in the record narrows the claims by prosecution disclaimer or amendment. That cuts both ways: the patent owner has no adverse PTAB estoppel or cancellation history to answer for, but it also has no validity credential — the claims have simply never been tested in a post-grant forum.

Estoppel landscape: essentially none, but the window has closed. Because no IPR/PGR was ever filed on the '694 patent, there is no § 315(e)(2) estoppel on any petitioner or privy — no prior art has been "used up." That sounds favorable to a defendant, but it is largely academic here: the structured data shows the patent expired 2019-05-03 ("Anticipated expiration", status "Expired – Lifetime"). An expired patent can still be the subject of an IPR in narrow circumstances, but the practical consequences for a defendant are dominated by the term, not by IPR availability. Note also that the expiration entry is expressly an assumption in the source data ("Anticipated expiration") — confirm the exact expiration and any term adjustment against the file history before relying on it in a damages analysis.

Pattern signals. No petitioner has filed even once against this patent, so there is no repeat-petitioner pattern; no Unified Patents or other defensive aggregator appears in the chain (the only well-known aggregator hit in my searches, Unified Patents, appeared in an unrelated IPR2022-00806 on a different patent). The patent's prosecution family links to a network of Fujitsu–HAL co-developed sparse-directory applications from the same 1998–1999 period (the '694 patent itself is in the same portfolio as the applications it cross-references, e.g. Ser. No. 09/281,714, "Split Sparse Directory," which issued as US 6,560,681, and U.S. Pat. No. 6,209,064 and 6,212,610). Google Patents also lists US 6,826,651 ("State-based allocation and replacement for improved hit ratio in directory caches") as a similar document — if a demand letter or assertion appears, check the assignee and priority chain of that neighbor separately; I have not verified that it shares an owner or priority with the '694 patent.

Recommended next steps

• No PTAB activity exists. Say so plainly to the client and in any litigation hold or defense strategy memo: there is no FWD to cite, no cancelled claim to rely on, and no IPR record to estop anyone. The absence is itself a signal about how (and how often) this patent has been asserted — a Fujitsu sparse-directory patent that has never drawn a single AIA petition.
• Pivot the defense to term, not validity. On the structured data, the patent was "Expired – Lifetime" as of 2019-05-03 (anticipated expiration). If a suit is threatened or filed now, map the § 286 six-year damages lookback against the expiration date — a complaint filed after the expiration date and more than six years after the last possible infringing act would have no recoverable damages window. Verify the exact expiration date (including any PTA/PTE) from the patent's own face and file history before committing to this position; the source data flags the date as an assumption.
• If you nevertheless need an invalidity or IPR option, the only claims you could currently challenge are the never-tested ones: independent claims 1 and 16 and their dependents. Grounds would start from the art already cited during prosecution — US 5,267,232 (IBM), US 5,377,345 (Sun), US 5,848,434 (Intel), US 5,897,655 (IBM), US 5,933,849 (AT&T), US 6,138,217 (Canon), US 6,185,658 (IBM) — plus the non-patent citations (the co-pending Fujitsu applications). Note that four of these seven were not available as § 102 art across the board given the 1998-05-08 priority date; several are § 102(a)/§ 102(e) candidates only. Any IPR should be budgeted against the reality that the patent owner cannot amend an expired patent and that the Board may weigh the expired status on discretionary grounds.
• No trial-stage milestones to track, because no proceeding is pending. There is no institution deadline, no oral hearing, and no statutory one-year FWD due date to monitor.
• Verify independently before relying. The record here rests on (a) an ODP structured block reporting zero AIA proceedings and (b) negative web search results. Before advising a client to skip PTAB work, re-run the search on the USPTO PTAB E2E / Patent Trial and Appeal Board docket and on CourtListener for any district court or Federal Circuit activity involving Fujitsu's sparse-directory family, since a district court invalidity judgment (not an IPR) is the one avenue that could still have narrowed these claims outside the PTAB. I found no such judgment, but I did not exhaustively search PACER.

Confidence. High confidence that no AIA trial proceeding is on file for US 6,625,694. Low confidence in any inference about district court litigation history involving this specific patent; that was not confirmed and should not be asserted without a PACER/docket check.

I'll verify the assignment record for US 6625694 against live sources before writing.

Let me check for any post-issuance assignments and Fujitsu's patent-holding structure.

Let me check Justia's assignment record and whether any Fujitsu portfolio transfers occurred.

Assignment & Ownership Analysis — US 6,625,694 (US 6625694)

Methodology note / limitation. The USPTO Assignment Center UI (assignmentcenter.uspto.gov, and its assignment.uspto.gov predecessor) could not be actively queried in this session; the searches returned no direct Assignment-Center record page for this patent. The assignment reconstruction below is grounded in (a) the "Legal Events" block of the authoritative Google Patents full text for US 6,625,694 B2, which records the single assignment event and its reel/frame, and (b) the Justia record. I was unable to retrieve the correspondent-of-record field for the one recording below; that field is flagged as unavailable rather than guessed. Anyone verifying should pull reel 009949/0250 on the Assignment Center directly.

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Inventors

Both inventors are named as assignors on the sole recorded assignment (reel 009949/0250) and are the same inventors on the co-pending Fujitsu applications cross-referenced in the specification (Ser. Nos. 09/003,721; 09/003,771; 09/041,568; 09/281,714; 09/285,316; 09/287,650). The specification describes a Fujitsu multiprocessor-node interconnect program (directory-based cache coherence, sparse directories), and the co-pending filings were all made by Fujitsu. On that basis both men were working on Fujitsu's US multiprocessor/server program at filing. Caveat: the assignment instrument itself does not state an employer relationship, and I did not independently confirm employment titles.

Unusual patterns: none detected. There is no evidence of either inventor leaving the assignee within 12 months of the 1999-05-03 filing. Weber's best-documented later career move (co-founding the network-on-chip company Arteris) occurred in the 2003 timeframe — roughly four years post-filing and well after the patent issued (2003-09-23).

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Original assignee

• Entity on the issued patent: Fujitsu Limited (Fujitsu Ltd), Kawasaki, Kanagawa, Japan — a large, publicly traded operating company.
• Primary line of business: computing/servers, telecommunications and IT systems, and (at the relevant time) semiconductors. The claimed subject matter — a memory controller with a sparse directory allocating entries under a state-preferring LRU replacement algorithm — is a server-chipset/coherence-controller feature, consistent with Fujitsu's multiprocessor server interconnect products of that era.
• Did they ship a product embodying the claims? Unclear / not confirmed. The specification is written as a hardware implementation (main memory, memory controller, sparse SRAM directory, per-processor bit-vectors), which indicates a real product program rather than a purely defensive filing, but I did not locate a specific Fujitsu SKU confirmation. The related cross-referenced Fujitsu applications strongly suggest the technology was implemented in a Fujitsu multiprocessor-node product line.
• Current status: Operating. Fujitsu Limited remains an active global IT services and computing company. No bankruptcy, and no assignment of this patent away from Fujitsu is recorded. The patent itself is Expired – Lifetime (full 20-year term ended 2019-05-03), so it is now in the public domain regardless of ownership.

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Assignment timeline

One recorded assignment total. Per the Google Patents legal-events record and Justia, this patent's only assignment is the original inventor→company assignment at filing.

• 1999-04-28 / 1999-04-29 (executed by assignors; the assignment shows signing dates 1999-04-28 to 1999-04-29) / recorded 1999-05-03 — Reel 009949 / Frame 0250
  • Conveyance: Assignment (Assignment of Assignors' Interest)
  • Assignor(s): Nabil N. Masri and Wolf-Dietrich Weber (the named inventors)
  • Assignee: Fujitsu Limited, Kawasaki, Kanagawa, Japan
  • Correspondent: Not retrieved. The Assignment Center correspondent-of-record field for reel 009949/0250 could not be pulled in this session; I will not guess it. (For calibration: a different Fujitsu recording, reel 009744/0813 on app. 09/192,003, shows the standard "reel/frame" assignment format Fujitsu's outside counsel used contemporaneously — but that is a different patent and is not evidence of the correspondent here.)
  • Context: Ordinary initial employment/company assignment — inventor-to-employer transfer at filing. Not a fire-sale, not an internal reorg, not a transfer-to-asserter.

There are no post-issuance assignments, no security interests, no mergers, no name changes, and no licensing records for this patent. Ownership has never left Fujitsu Limited.

(Note on a red herring: the string "US-6625694-" appears inside a PTAB/petition document at ptacts.uspto.gov, but that document concerns a different application — Ser. No. 12/121,531, Rozas, "Memory Management for Cache Consistency" — and "6625694" appears only as a search term in a query-log table. It is not an assignment record and not evidence of any transfer.)

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Timeline diagram

timeline
    title Ownership of US 6625694
    1998 : Provisional filed by two inventors
    1999 : Utility application filed
         : Assigned to Fujitsu Limited
    2003 : Patent issued
    2019 : Twenty year term ended

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NPE / troll-pattern signals

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Verdict

Insufficient data — and specifically the benign variant: only the original assignment exists.

The instruction's "Insufficient data" category is defined as "no records, or only the original assignment," which is exactly this case: there is a single recorded conveyance (inventors Masri and Weber → Fujitsu Limited, executed 1999-04-28/29, recorded 1999-05-03, reel 009949/0250) and nothing thereafter. All eight NPE signals are not present, the patent never left its original operating-company owner, no assertion activity was found, and the patent lapsed with the natural end of its 20-year term on 2019-05-03 (Google Patents status: Expired – Lifetime; maintenance fees paid at years 4, 8, and 12). This is the profile of a dormant, fully-owned, now-expired corporate patent, not an NPE vehicle.

Verification links: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (search patent number 6625694; the loading record is reel 009949/0250). Google Patents legal events — https://patents.google.com/patent/US6625694/en. Justia — https://patents.justia.com/patent/6625694.

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Residual uncertainties (stated plainly)

1. Correspondent of record for reel 009949/0250: not retrieved. This is the one data element the task specifically asked me to capture carefully, and I could not obtain it in this session. It should be pulled directly from the Assignment Center's record page for that reel/frame.
2. Inventor employer titles are inferred from the co-pending Fujitsu applications and the assignee, not from a stated employment designation.
3. Product embodiment of the claims by Fujitsu is inferred from the hardware-oriented specification and the Fujitsu server-interconnect program, not confirmed against a product document.
4. Absence of a found lawsuit is not proof that none was ever filed; it simply did not surface in the sources checked.

I'll verify the patent in the USPTO database and research each cited reference.

Let me research the remaining cited references.

Let me research the remaining three references.

Prior-Art Analysis — US 6,625,694 B2

Scope note: This section builds on the verified identification of the patent (US 6,625,694 B2; App. 09/304,432; priority 1998‑05‑08; filed 1999‑05‑03; granted 2003‑09‑23; Fujitsu, inventors Masri & Weber). It does not repeat the summary/claims/algorithm sections. The "prior art" examined here is the set of references cited on the face of the patent (7 U.S. patents) plus the 4 non‑patent citations, as listed in the authoritative Google Patents / USPTO record.

One framing point that governs everything below: because App. 09/304,432 was filed 1999‑05‑03 with a 1998‑05‑08 priority date, it is a pre‑AIA application. Prior art therefore arises under pre‑AIA § 102(a)/(b)/(e). Critically, several cited references did not publish until after the May 1998 priority date — they are only available as prior art under § 102(e) (a U.S. patent granted on an application filed before the applicant's invention date is prior art as of its filing date). That distinction is noted for each reference.

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A. The two most relevant references

1. US 5,897,655 A — the single closest reference

• Full citation: System and method for cache replacement within a cache set based on valid, modified or least recently used status in order of preference, US 5,897,655 A; assignee International Business Machines Corp.; filed 1996‑12‑10; granted 1999‑04‑27 (Google Patents: https://patents.google.com/patent/US5897655).
• Description: A set‑associative data/instruction cache (an enhanced PowerPC 603e‑class processor, 16 KB, 4‑way, 128 sets) in which the replacement logic selects a victim according to an ordered preference of coherency status: (i) an entry that is valid/available (invalid) is preferred; then (ii) an entry in the modified (dirty) state; then (iii) fallback to LRU. Each block carries MESI state bits plus LRU status bits. This is the same triage strategy — use a free entry first, otherwise rank candidates by coherence state, and use LRU as the tie‑breaker — that the ’694 patent claims, and it predates the ’694 priority date by ~17 months (filing date 1996‑12‑10 controls under § 102(e)).
• Claims potentially anticipated (as a § 102 reference, subject to full element‑by‑element comparison): 1, 4, 5, 6, 11, 13, 16, 17, 20, 21. Specifically, it discloses the "available entry first" step (claims 4, 17), a "modified/dirty" candidate (claims 6, 20), and LRU‑from‑the‑highest‑ranked‑class selection (claims 3, 19, 21). Its entry format (address tag + MESI state + LRU bits) maps closely onto claim 11's "state information field … tag field."
• Key gap that likely defeated anticipation: US 5,897,655 orders invalid → modified → LRU; it does not expressly teach the ’694 shared‑before‑dirty ranking (claim 2 / claim 18) and, being a single‑processor cache, does not use a sparse directory sized smaller than main memory with a bit‑vector of sharing caches (claim 1) or the retry‑when‑all‑entries‑are‑transient step (claims 1, 16). That combination is what distinguishes the ’694 invention.

2. US 6,185,658 B1 — victim selection driven by coherency state

• Full citation: Cache with enhanced victim selection using the coherency states of cache lines, US 6,185,658 B1; assignee International Business Machines Corp.; filed 1997‑12‑17; granted 2001‑02‑06 (Google Patents: https://patents.google.com/patent/US6185658; full text PDF: patentimages…US6185658.pdf).
• Description: An SMP multi‑level cache hierarchy (L1/L2/L3, PowerPC‑based) applying the principle of inclusion, with MESI‑type per‑block state, snooping over a generalized interconnect, "snoop‑push," a "shared/not‑shared" indication returned on reads, and a "retry" message when a requested block must first be retrieved from a higher cache level. The invention's point is enhanced victim selection that takes the coherency states of the cache lines into account — i.e., choosing the line to evict based on that line's coherence state rather than LRU alone.
• Claims potentially anticipated: 2, 6, 9, 10, 14, 15 (and method analogues 16, 23, 24). It explicitly discloses excluding special/transient states from eviction and reasoning about shared vs. modified/exclusive state during replacement; the "retry" behavior it describes is the functional counterpart of the ’694 retry step (claims 1, 16).
• Key gap: It addresses a hardware multi‑level cache (inclusion) victim policy, not a sparse directory of cache‑coherence entries; the § 102(e) date (1997‑12‑17) is later than US 5,897,655's, so it is a secondary rather than lead reference.

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B. Remaining cited U.S. references (in citation‑table order)

3. US 5,265,232 A

• Full citation: Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data; inventors Gannon et al.; assignee International Business Machines Corp.; App. 07/679,900; filed 1991‑04‑03; granted 1993‑11‑23 (https://patents.google.com/patent/US5265232).
• Description: A cross‑invalidate (XI) coherence directory shared by processors, having entries with a valid field, address field, CPID (per‑processor) bit field, and an EX/RO ownership field. Notably, its claim 5 recites set‑associative congruence classes with replacement means that select the entry having the least number of CPID bits set on, and if tied, select any such entry. It also teaches "EX‑aged" handling for lines aged out of a private cache — i.e., recognition of stale directory information.
• Claims potentially anticipated: 5, 10/24, 11, 13, 14. Its "least number of CPID bits set" replacement heuristic is a sharing‑aware preference conceptually aligned with the ’694 preference for evicting shared entries; its CPID bit vector maps onto claim 11's per‑processor bit‑vector field; its "EX‑aged"/stale handling maps onto claim 14 (stale shared entry).
• Gap: It selects on number of sharers, not on a three‑level invalid → shared → dirty state hierarchy, and it has no all‑transient retry step.

4. US 5,848,434 A

• Full citation: Method and apparatus for caching state information within a directory‑based coherency memory system; inventors James, Young, Stevens; assignee Intel Corp.; App. 08/762,636 (US19960762636); filed 1996‑12‑09; granted 1998‑12‑08 (Espacenet: https://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=[5848434A](/patent/5848434A)).
• Description: An eight‑processor SMP system with a "state cache" memory that stores coherence state for only a fraction (e.g., 1/16) of the memory lines, because rarely is all of memory cached at once — a direct‑mapped cache storing state + tag, indexed by address bits. This is precisely the "sparse directory containing fewer entries than the main memory has memory lines" concept of ’694 claim 1. Its companion EP 0 847 011 A3 (same family; "Method for reducing the number of coherency cycles…") further addresses replacement of state‑cache entries and a default SHARED state with castout handling for OWNED lines.
• Claims potentially anticipated: 1, 11, 12, 13. It strongly supports claim 1's sparse‑directory limitation and the notion of "caching state information"; the "additional coherency actions resulting from replacements of cached state entries" passage speaks directly to the eviction problem the ’694 invention addresses.
• Gap: It is a direct‑mapped state cache and does not disclose the ordered invalid → shared → dirty (LRU) → retry replacement algorithm; its § 102(e) date (1996‑12‑09) is one day earlier than US 5,897,655's.

5. US 5,377,345 A

• Full citation: Methods and apparatus for providing multiple pending operations in a cache consistent multiple processor computer system; assignee Sun Microsystems, Inc.; filed 1992‑04‑29; granted 1994‑12‑27 (per the patent's face citation table).
• Description (from the citation record; I was unable to retrieve the full specification text): Mechanisms for sustaining multiple in‑flight (pending) memory/coherence operations while preserving cache consistency in a multiprocessor — relevant background for the concept of lines being "in transition," which underpins the ’694 retry step.
• Claims potentially anticipated: 9, 16 (retry/transitional‑state aspect only). As a § 102(b) reference it is unquestionably prior art on date, but on the citation‑table description alone it does not disclose the claimed state‑ordered directory‑entry allocation; it is more useful as a § 103 secondary reference than as an anticipation reference.
• Caveat: I could not obtain the full text in this session; treat the anticipation mapping as tentative.

6. US 5,933,849 A

• Full citation: Scalable distributed caching system and method; assignee AT&T Corp.; filed 1997‑04‑10; granted 1999‑08‑03 (per the patent's face citation table).
• Description (from the citation record; full text not retrieved): A distributed, scalable caching architecture — background for large‑scale directory‑based coherence and for why a full, memory‑sized directory is impractical, motivating the sparse directory of claim 1.
• Claims potentially anticipated: 13, 15 at most (scalable caching / discard‑of‑unneeded data), and these only weakly.
• Caveat: Same full‑text limitation as above; qualifies under § 102(e) from 1997‑04‑10.

7. US 6,138,217 A

• Full citation: Method and apparatus for cache coherency in an interconnecting network; assignee Canon Kabushiki Kaisha; App. filed 1996‑11‑25; granted 2000‑10‑24 (per the patent's face citation table).
• Description (from the citation record; full text not retrieved): Cache‑coherency mechanisms for an interconnected (networked) multiprocessor — the same "multiprocessor‑node" setting as the ’694 invention, and a § 102(e) reference as of its 1996‑11‑25 filing date.
• Claims potentially anticipated: background for claims 1 and 16 (networked coherence) only; I did not find disclosure of the state‑ordered allocation or retry features.
• Caveat: Full text not retrieved; mapping tentative.

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C. Non‑patent citations (co‑pending applications)

These four are the applicant's own co‑pending applications, cited in the ’694 specification as incorporated by reference (not as § 102 prior art against it, but as the surrounding system context):

The "Split Sparse Directory" application (09/281,714) is the most technically adjacent: it supplies the sparse‑directory substrate whose entry‑allocation policy the ’694 patent claims.

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D. Bottom line

• Most relevant prior art: US 5,897,655 A (ordered replacement by valid/modified/LRU status in order of preference) is by far the closest — it is the only cited reference that teaches state‑ranked victim selection with an LRU tie‑breaker, and it predates the ’694 priority date (effective § 102(e) date 1996‑12‑10). US 6,185,658 B1 (victim selection using coherency states) is the next closest.
• The feature that no single cited reference shows in combination: the ’694 claims tie the eviction policy to a sparse directory whose primary ranking is invalid → shared → dirty, with retry when every entry is transient (claims 1 and 16). US 5,897,655 supplies the ordered‑preference idea but ranks modified ahead of the LRU fallback and lacks the shared‑preference and sparse‑directory/retry elements; US 5,848,434 supplies the sparse state cache but not the algorithm; US 5,265,232 supplies a sharing‑count replacement heuristic but not the state hierarchy. This is consistent with the patent having issued over all seven references — the examiner evidently found the specific combination unobvious rather than anticipated.
• § 102 hierarchy I would assign: US 5,897,655 (claims 1, 4, 5, 6, 16, 17, 20, 21) > US 6,185,658 (claims 2, 6, 9, 10, 14, 15) > US 5,848,434 (claim 1's sparse directory) > US 5,265,232 (claims 5, 11, 13, 14) > the remaining three as § 103/background only.

Explicit uncertainties: (i) I could not retrieve full specification text for US 5,377,345, US 5,933,849, and US 6,138,217 in this session; their descriptions and any claim mapping rest on the patent's own face‑citation table (title/date/assignee) and should be confirmed against the full documents before being relied on. (ii) The § 102(e) analysis assumes a pre‑AIA filing regime and that the cited applications' U.S. filing dates are the controlling § 102(e) dates; where a reference claims an earlier foreign or provisional priority, its § 102(e) date could differ (pre‑AIA § 102(e) generally uses the U.S. filing date, so foreign priority would not advance it). (iii) "Potentially anticipates" here means discloses elements relevant to the recited claims — true anticipation requires every element of a claim in a single reference, which, as noted, no single cited reference achieves for the independent claims.

I'll verify the key prior-art references from the "Citations" section before building the §103 analysis, since the reference titles alone are suggestive but I want firmer grounding on what each actually discloses.

Obviousness Analysis — US 6,625,694 B2 under 35 U.S.C. § 103

Patent: US 6,625,694 B2 — "System and method for allocating a directory entry for use in multiprocessor-node data processing systems"
Applicants/Assignee: Fujitsu Limited · Inventors: Masri, Weber
Priority: 1998‑05‑08 · Filed: 1999‑05‑03 · Granted: 2003‑09‑23 · Expired – Lifetime: ~2019‑05‑03

Building on the prior sections: the summary and litigation sections above are treated as authoritative and are not repeated. As those sections concluded, no litigation or 2026 CAFC/PTAB activity against this patent was located; accordingly, this § 103 analysis is directed at (a) prosecution-history/reexam-style defensibility and (b) defensive/validity opinions, not at an identified live dispute.

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1. Method, scope, and explicit caveats

Framework applied. I use the Graham v. John Deere factors: scope and content of the prior art, differences between the prior art and the claims, level of ordinary skill, and secondary considerations. For the combination step I apply KSR Int'l v. Teleflex (obvious to try; predictable results; design incentives; known techniques applied to a known structure) and the In re Keller / In re Merck rule that a combination is not taught away merely because each reference addresses a different sub-problem.

Level of ordinary skill in the art (POSITA). A B.S. in electrical engineering or computer science (or equivalent), plus roughly 2–5 years of experience designing cache-coherence hardware or directory protocols, or an M.S. with ~2 years — i.e., a person who reads Hennessy & Patterson and the MESI/MOESI literature as routine background. The '694 specification itself treats multi-way set-associative caches, MESI-style states, and LRU replacement as old and well known, which supports this framing.

Caveats — read these before relying on any single mapping:

1. I was given the full authoritative text of US 6,625,694. For the references, I had the "Citations (7)" list, the "Non‑Patent Citations (4)" list, and whatever full-text/abstract material I could retrieve live (Google Patents, FPO, EPO, uspto.report). I retrieved substantive text for US 5,897,655; US 6,185,658; US 5,848,434 (and its EPO sibling EP 0 847 011 B1 / DE 69736544 T2); US 5,265,232; US 5,377,345. I did not retrieve usable full text for US 5,933,849 (AT&T) or US 6,138,217 (Canon); those are treated below as supplementary references only, on the strength of their titles.
2. Where I state that a reference "discloses" an element, I am mapping from the reference's title, abstract, and retrieved passages — not from a full element-by-element reading of every independent claim of that reference. A formal opinion should confirm each mapping against the full specification and claims.
3. Specific caution on US 5,897,655. Its title states that replacement is "based on valid, modified or least recently used status in order of preference." The direction of that preference ordering should be verified against the '655 specification before relying on it to teach the "shared-before-dirty" ranking of claim 2. As discussed in § 5, the direction is supplied independently by US 6,185,658 and by an explicit engineering rationale, so the analysis does not hinge on this point — but do not overstate it.
4. One identifier note carried over from the prior sections: the literal number 6625694 is correct for this patent; it has been confused elsewhere with an unrelated FDA FAERS case number and with a PTAB search string. No auto-correction applied.

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2. The inventive core, decomposed

Stripping the claims to their inventive weight (the preamble hardware — main memory, per‑processor caches, a memory controller, a multi-way directory entry format — is largely admitted prior art in the specification itself):

The only genuinely "new-looking" kernel is E3+E4+E7 — i.e., a directory (not cache) replacement policy that ranks candidates by coherence state, prefers shared over dirty for cost reasons, and retries rather than evicts when everything is transient. Everything else (E1, E2, E5, E6, E10–E12) is squarely in the cited art.

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3. Reference-by-reference disclosure map (from the page's Prior Art section)

A. US 5,897,655 A — IBM — "System and method for cache replacement within a cache set based on valid, modified or least recently used status in order of preference" (filed 1996‑12‑10; issued 1999‑04‑27).
Retrieved text confirms: 4‑way set-associative cache (128 sets), each block storing an address tag, "MESI state bits" and "LRU status bits." The title identifies precisely the three criteria the '694 claims use — validity, modified/dirty status, and LRU — applied as an ordered preference. This is the closest single reference to the '694 selection policy (E2, E3, E5, and the raw material for E4). Its only real gap: the victim is a cache line in a processor cache, not an entry in a shared sparse directory.

B. US 6,185,658 B1 — IBM — "Cache with enhanced victim selection using the coherency states of cache lines" (filed 1997‑12‑17; issued 2001‑02‑06).
Retrieved text confirms the reference is directed to victim selection keyed to coherency state, and — importantly for E7 — discloses a retry mechanism: "the L3 cache places a message on the generalized interconnect informing the processing unit that it must 'retry' its operation again at a later time, because the actual value of the memory location is in the L1 cache … and must be retrieved." It also discusses the "shared"/"not shared" indication, inclusion, and stale lower-level copies — i.e., the stale-entry environment of E13. This reference supports E2, E3, E7, E13.

C. US 5,848,434 A — Intel (NCR-developed) — "Method and apparatus for caching state information within a directory-based coherency memory system" (filed 1996‑12‑09; issued 1998‑12‑08), and its EPO sibling EP 0 847 011 B1 / DE 69736544 T2.
Retrieved abstract/text: a directory-based coherency memory system with a shared system memory, a data cache per processor, and a "state cache memory" holding line-state information for only a portion of the memory lines — e.g., one sixteenth — "in recognition that rarely will all of system memory be utilized (cached) at any one time." The state cache is direct-mapped, storing a tag field taken from a first portion of the address and indexed by the remaining portion. The EPO sibling's claims recite a "method for replacing entries within a state cache memory," including a default SHARED state and a castout when the cached state is OWNED, expressly to "reduce the number of coherency operations caused as a result of replacements." This reference supplies E1, E11, and the sparse-directory replacement setting, plus a cost-based rationale for preferring shared entries (supports E4).

D. US 5,265,232 A — IBM — "Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data" (filed 1991‑04‑03; issued 1993‑11‑23).
Retrieved text confirms: an XI (cross-invalidate) directory shared by processors; the directory records which processors hold a copy and invalidations are targeted (no broadcast). Its per-CPU tracking is expressly a bit-vector-style structure ("WSV comprises eight bits that respectively correspond to the CPUs in the system") — supports E10. Critically, it states the invalid-first / evict-with-castout policy almost verbatim: "the cache assignment of a location for the new data unit will be in a cache location not in current use if one can be found. If all of the useable cache locations are currently occupied with changed data units, then one of them must be reassigned … But before the new data unit can be written into the cache location, a castout to main memory is required of the updated cache data unit." That is the '694 FIG. 7 steps 1004→1010→1020 in substance. Supports E2, E3, E4, E6, E10.

E. US 5,377,345 A — Sun Microsystems — "Methods and apparatus for providing multiple pending operations in a cache consistent multiple processor computer system" (filed 1992‑04‑29; issued 1994‑12‑27).
Retrieved text: the external cache directory has per-subblock status fields including a "pending-bit" which, when set, indicates a pending uncompleted outstanding operation on a subblock," and "a set pending-bit will prevent the CPU from accessing data presently stored in the corresponding subblock." It also discloses retry behavior for operations that cannot proceed ("the CPU will retry the operation until the I/O count … is zero"). Supports E7, E8, E9.

F. US 5,933,849 A — AT&T — "Scalable distributed caching system and method" (filed 1997‑04‑10; issued 1999‑08‑03). Full text not retrieved; title/scope only. Supports the general motivation for a scalable (sparse/hashed) directory rather than a full per-line directory (E1).

G. US 6,138,217 A — Canon — "Method and apparatus for cache coherency in an interconnecting network" (filed 1996‑11‑25; issued 2000‑10‑24). Full text not retrieved; title/scope only. Supplementary for multiprocessor-network coherence context.

Non-patent citations (incorporated into '694 by reference).

• US App. 09/281,714, Wilson, "Split Sparse Directory for a Distributed Shared Memory Multiprocessor System" (later US 6,560,681) — directly evidences that the sparse/split directory of E1 was a known, co-pending design choice in the very same program.
• US App. 09/003,721 (Cache Coherence Unit …), 09/003,771 (Memory Protection …), 09/041,568 (Weber, Pipelined Snoopy Protocol, later US 6,631,448), 09/285,316, 09/287,650 — co-pending Fujitsu work evidencing that the surrounding coherence hardware was conventional to a POSITA by the 1998 priority date.

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4. Primary § 103 grounds

Ground 1 (principal): US 5,897,655 in view of US 5,848,434, further in view of US 5,265,232 and US 6,185,658 — renders claims 1–8, 11–14, 16–23 obvious

What the combination yields:

Motivation to combine.

1. Same field, common problem. Both '655 and '434 address replacement in a coherence-maintained, multi-processor memory hierarchy; '658 is expressly about coherency-state-driven victim selection.
2. Predictable, mechanical substitution. '655's policy (rank candidate entries by coherence state, then LRU) is separable from the array it operates on. Applying that policy to '434's state cache/directory — which is the entity '434 already replaces entries in — is the application of a known technique to a known structure, yielding no change in the technique's operation and no unexpected result (KSR).
3. Explicit design incentive, quantified. '434/EP 0 847 011 states the goal in the '694's own terms: reduce coherency traffic caused by replacements. The '694 specification gives the identical rationale (evicting a shared entry costs only an invalidation; evicting a dirty entry costs a write-back). Where the reference and the patent articulate the same benefit, motivation is established a fortiori.
4. Both '655 and '434 are on the face of '694 — the examiner already had them; the ground is built from references the applicant did not distinguish.
5. Two of the references share an assignee ('655 and '658, IBM) — combinability of commonly-owned, same-field references is not seriously contestable.

Ground 2 (alternative principal, strongest on E7): US 6,185,658 in view of US 5,848,434 — renders claims 1, 2, 5, 6, 7, 9, 14, 15, 16, 22 obvious

'658 is titled for "enhanced victim selection using the coherency states of cache lines," and adds the retry teaching that Ground 1 borrows from it. Paired with '434's sparse state cache (and its express state-cache replacement method), this combination reads on claim 1 almost element-for-element, including the "all entries transient → retry" limitation: '658 teaches that when coherence resolution cannot complete, the requester is told to retry; '345 generalizes retry to entries flagged pending. A POSITA who has already adopted state-based victim selection would find it obvious to decline to evict in-flight (transient) entries — because their coherence transactions are unsettled — and to instruct the requester to retry, exactly as '658 and '345 each do.

Ground 3 (E13 — stale entries): US 5,848,434 / US 6,185,658 in view of the '694 specification's own admissions

Claims 14–15 (stale directory entries; using the directory to identify discardable stale data) are addressed by the specification's own characterization of the environment: it states that "for various reasons, a cache 110 may replace its cached line without updating the corresponding directory 224 entry," and '658 discusses stale lower-level copies coexisting with a modified higher-level copy. An admission about the prior-art environment in the specification can be used against the claims. Absent that, E13 is at least strongly suggested by any inclusion-based directory.

Ground 4 (E12/E1 scalability): US 5,933,849 in view of US 5,848,434

If a primary reference is needed for the scalability motivation behind a sparse directory, '849's title ("Scalable distributed caching system and method") supplies it. Do not over-rely on this ground — I could not retrieve '849's text.

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5. Motivation to combine, stated in KSR terms

• Predictable results / obvious to try. The field had a small, enumerable set of replacement policies (LRU, FIFO, random, state-preferenced). '655 and '658 each already pick "state-preferenced + LRU." Extending the same policy to a directory cache is the obvious next application.
• Design incentive. Eviction cost is asymmetric: invalidating a shared entry = a coherence message; evicting a dirty entry = a data write-back. Ranking shared above dirty therefore directly serves the universally desired goal of minimizing off-chip traffic. '434/EP 0 847 011 says so.
• No teaching away. '655's title ordering should be verified (§1 caveat 3); even if '655's preference order differs in direction, it is directed to a processor cache set, and a reference teaches away only if it criticizes, discredits, or otherwise discourages the claimed approach. Nothing retrieved from '655, '658, '434, or '232 discourages state-ranked directory replacement; '232 in fact endorses the invalid-first/evict-dirty-with-castout flow.
• Reasonable expectation of success. All components are hardware-standard: coherence state bits and LRU bits per directory entry, a direct-mapped or set-associative state cache, a bit vector of sharers, and a retry/nack path — all disclosed (E10, E11 in '232/'434) or admitted as conventional by the '694 specification.

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6. Claim-by-claim chart (principal grounds)

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7. Where a validity defense would push back (and how strong it looks)

1. The retry-on-all-transient limitation (claims 1, 16). This is the best non-obviousness candidate. Neither '584/EP 0 847 011 nor '655 is a directory that refuses to evict; the references retry for other reasons (a modified line lives in a higher cache; a subblock is pending). A patentee could argue that the combination of (i) a sparse directory, (ii) state-ranked replacement, and (iii) a global "all transient → retry" escape was not suggested. Counter: '658 and '345 each teach retry on an unavailable/pending resource, and refusing to evict entries whose coherence transactions are in flight is a straightforward application of '345's pending-bit teaching. Strong but not overwhelming § 103 ground; a full-text reading of '658 and '345 is required to firm it up.
2. Claim 10/24 ("shared states have a hierarchical level separate from other states"). If construed to require multiple distinct shared sub-states, EP 0 847 011's SHARED BUS A / BUS B / SHARED BOTH hierarchy is relevant (and arguably closer to anticipation than obviousness). If construed merely as "shared is its own tier," it collapses into claim 2. Construing this term is a threshold issue.
3. Claims 14/15 (stale entries). The mapping is inferential and depends on using the specification's own admissions about a stale-entry environment. Treat as the weakest ground.
4. Secondary considerations. None are evidenced on this record. The patent has been expired since ~2019‑05‑03 with fees paid at years 4, 8, and 12 and no located assertion or challenge (see prior sections). Absent nexus evidence, objective indicia are unlikely to overcome even a moderate prima facie case. Caveat: absence of located litigation is not proof of absence (the prior section flagged incomplete database coverage), and commercial success, if any, would need to be tied by nexus to the claim elements.

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8. Bottom line

• Claims 1–9, 11–13, 16–24 are, in my assessment, likely obvious under § 103 over US 5,897,655 in view of US 5,848,434 (its EPO sibling EP 0 847 011 B1 supplying the express state-cache replacement method and the shared-first cost rationale), with US 6,185,658 and US 5,377,345 supplying the retry/transient teaching and US 5,265,232 supplying targeted invalidation, the per-processor bit vector, and the invalid-first/castout flow.
• The single most defensible claim element is the "all entries transient → retry the request" limitation of independent claims 1 and 16. It should be attacked with '658 + '345 as the retry references; a full-text verification of both is the highest-value next step.
• Claims 14 and 15 are the weakest mappings and should not be relied upon without the specification-admission theory.
• Claims 10 and 24 turn on claim construction of "hierarchical level," which should be resolved before asserting or attacking them.

Recommended verification before filing any paper: pull the full specifications of US 5,897,655 (to fix the direction of its preference ordering) and US 6,185,658 and US 5,377,345 (to confirm the retry and pending-bit teachings), and obtain US 5,933,849 and US 6,138,217 text, which I could not retrieve. Everything above that rests on titles/abstracts alone is flagged in § 1 and should be upgraded to full-text support or dropped.