US 6262702

I'll search for information about this patent number as requested.

Let me search specifically for CAFC litigation and USPTO records.

US Patent 6,262,702 — Analyst Summary

Important caveat on sources: I searched for USPTO and CAFC 2026 docket records for this exact number. The CAFC-specific searches returned no results — I found no 2026 Federal Circuit docket, appeal, or IPR activity referencing 6,262,702. I therefore cannot confirm any litigation/appeal; absent authoritative records, treat that as "none found," not "none exists." The bibliographic and claim data below come from the Google Patents and Justia records for US6262702 (and are consistent with the authoritative full text supplied to me).

Bibliographic data

Abstract

I could not retrieve the verbatim abstract text from the sources, so I will not fabricate it. In substance, the disclosure addresses an active-matrix (TFT) liquid-crystal electro-optical apparatus in which the high-frequency data-line clock signal (e.g., CLX/CLX′) is electrically shielded from the image-signal lines (VID1…VID12) by an electrically conductive line held at a constant potential (the drive-circuit power-supply wirings VSSX/VDDX/VSSY/VDDY), preventing high-frequency clock noise from degrading the sampled image/data signals. Note the Google Patents "prior art keywords" for this record are: line, lines, data, substrate, image signal.

Independent claims (plain language)

The record shows at least two independent claims, claim 1 and claim 11 (the specification frames these as the "first aspect" and "second aspect," with an additional scanning-line-power-supply aspect that may be a further independent claim — I could not confirm the full claim set, so treat the third aspect as uncertain).

Claim 1 (first aspect) — shielded signal-line architecture:
An electro-optical apparatus having a substrate carrying: scanning lines; intersecting data lines; switching elements (TFTs) at the intersections; pixel electrodes driven by those switches; a data-signal supply circuit that outputs data signals to the data lines in response to a clock signal; an image-signal line feeding the image signal (from a first external terminal) to that supply circuit; a clock-signal line feeding the clock signal (from a second external terminal) to that supply circuit; and an electrically conductive line held at a constant potential that shields the image-signal line from the clock-signal line. Independent purpose: suppress high-frequency clock noise coupling into the image signal.

Claim 11 (second aspect) — split/balanced image-signal-line routing with shielding:
An electro-optical apparatus with data lines, scanning lines, switching elements, pixel electrodes, multiple image-signal lines split into a first group and a second group, control-signal lines carrying control signals including a clock signal, and a data-signal supply circuit that receives the image and control signals and supplies corresponding data signals to the data lines. The first group of image-signal lines runs to one side of the data-signal supply circuit and the second group runs to the opposite side, with at least one electrically conductive line shielding both groups from the control-signal lines. Independent purpose: distribute the many image-signal lines in a well-balanced way around the driver (fixing the "wiring concentrated on one side" problem) while shielding them from clock noise.

Notable dependent claims (for context)

• 5–6: Third external input terminal placed between the first (image) and second (clock) terminals; the conductive shield extended to surround the image display area and data lines.
• 7: Shield portion placed opposite a light-shielding frame on the counter substrate (space-efficient shielding).
• 8–9: Shield and data lines formed of the same low-resistance metal (e.g., Al) in the same plane/process step.
• 10: A capacitance (storage) line connected to the conductive shield.
• 12–14: Shielding directed specifically at high-frequency control lines (period shorter than the horizontal scanning period), with low-frequency control lines (e.g., start signal DX) optionally co-routed as additional spacing; and a specific external-input-terminal ordering (first/second image groups flanking the third control terminals, with fourth shield terminals between).

Bottom line

This is a 1998-filed Seiko Epson patent (issued 2001) covering shielding image-signal lines from high-frequency clock lines using constant-potential power-supply conductors, plus balanced dual-side routing of image-signal lines around the data-line driver. It is expired, and I found no CAFC 2026 docket activity for it. If you need the verbatim abstract or an exhaustive claim set, I'd recommend pulling the granted-claims text directly from USPTO PatentCenter/Global Dossier for application 09/331,841, since the sources I reached did not expose the full text.

I'll search for litigation involving US patent 6262702 specifically.

Let me search more targeted sources for litigation on this specific patent.

Let me run more targeted searches on patent litigation databases for this exact patent number.

Litigation Search Results for U.S. Patent No. 6,262,702

No litigation involving U.S. Patent No. 6,262,702 was identified in the sources searched.

I ran multiple targeted searches (Google Patents, Federal Circuit materials, ITC publications, CourtListener/PACER-derived documents, and patent-litigation aggregator content surfaced via the Unified Patents / RPX / Docket Alarm ecosystems). None of the results tie any lawsuit, ITC investigation, PTAB proceeding, or Federal Circuit appeal to U.S. Patent No. 6,262,702 specifically.

Important caution about false positives

Several search hits referenced a "'626 patent," but a review of the text shows these are different patents and must not be conflated with 6,262,702:

• Oren Technologies / PropX — Federal Circuit appeal No. 19-1778 (2021) and related PTAB proceedings involving a "proppant container" '626 patent. This is an unrelated patent (subject matter: intermodal hopper containers for proppant), not 6,262,702.
• BSLLC v. Siemens-related ITC/district court matter — an unrelated "'626 patent" concerning semiconductor EDA design tools.

Per your instruction, I am not treating these as litigation of U.S. 6,262,702.

Patent context (from the authoritative full text provided)

• Patent: US6262702B1 — "Electro-optical device and electronic apparatus"
• Inventor: Masao Murade
• Assignee: Seiko Epson Corporation
• Priority date: 1997-10-31; Filed: 1998-10-23; Granted: 2001-07-17
• Application: US09/331,841
• Legal status: Expired – Lifetime (anticipated expiration 2018-10-23)
• A related continuation/divisional, US6483493B2 (from US09/828,965), is noted as a priority-linked family member.

This is a fairly old (1997-priority), expired Seiko Epson display/TFT-array patent. Expired status and age make it unlikely to have been asserted in recent NPE or competitor litigation, which is consistent with the absence of hits.

Caveats on completeness

• I could not complete exhaustive dedicated queries against paid/registration-walled litigation databases (e.g., Unified Patents litigation caselist, Docket Navigator, full PACER dockets) before hitting the tool-call limit. My conclusion rests on the public search results actually retrieved.
• The searches I ran did not return a definitive "no cases filed" statement from a litigation database; rather, they returned no matches linking this specific number to any case.
• Recommendation for verification: directly query the Unified Patents litigation caselist, Docket Navigator, Lex Machina, and PACER for "6,262,702," and check the USPTO Patent Center / Assignment records and the ITC EDIS database. If you can share access or a specific docket, I can drill into any candidate case.

Bottom line: Based on the searches performed, there is no known litigation involving U.S. Patent No. 6,262,702. If precise confirmation is required, the number should be run directly against the subscription litigation databases named above, since my results are not a certified negative.

I'll verify the structured block's "no proceedings" default against live sources before reporting.

PTAB proceedings on file

No AIA trial proceedings on file for US 6,262,702.

I ran the ODP-derived structured block (the canonical list you supplied) and independently searched for any IPR/PGR/CBM petition, institution decision, Final Written Decision, or Federal Circuit appeal naming this patent or its assignee. The structured block returned zero proceedings, and live web searches surfaced nothing — no petition papers on PTACTS, no FWD at the PTAB Decisions site, no CAFC opinion, no CourtListener docket, no Unified Patents or RPX filing. The only relevant hits were third-party documents citing different patents also numbered "702" (e.g., U.S. 11,671,702 in an unrelated camera-patent IPR, and 11,874,702 in PGR2024-00039). Those are not this patent. Do not cite them as proceedings on US 6,262,702.

{NONE} — No proceedings identified

• Type: N/A — no Inter Partes Review, Post-Grant Review, or Covered Business Method review identified
• Filed: N/A
• Status: Verbatim from the structured data: no AIA trial proceedings returned by the USPTO Open Data Portal as of the most recent ingest
• Judge panel: N/A — no panel ever convened
• Petition grounds: N/A
• Institution decision: N/A
• Final Written Decision: N/A — note that because no IPR was ever instituted, no claim of 6,262,702 has ever been canceled, confirmed, or construed by the Board
• Settlement / termination: N/A
• Appeal: N/A — no PTAB decision, therefore no CAFC appeal
• Defensive value: The Board has never touched this patent. There is no FWD to lean on, no claim-cancellation leverage, and no § 315(e)(2) estoppel to leverage or fear. Any IPR defense would have to be built from scratch on prior art you locate yourself.

Strategic summary

Claim status: entirely UNTESTED. No claim of US 6,262,702 has been canceled, sustained, or even construed in an AIA trial. There is no "surviving claim set" narrowed by PTAB — the claims as issued stand unscathed, not because they were validated, but because nobody asked the Board to review them. I cannot tell you which claims are strong or weak; there is no PTAB record to read.

The real defensive story here is timing, not validity. Per the structured data, the patent's anticipated expiration is 2018-10-23 and its legal status is Expired – Lifetime. That single fact dominates everything else: an expired patent cannot be infringed by post-expiration conduct, and damages exposure for pre-expiration conduct is subject to the 35 U.S.C. § 286 six-year lookback — which itself lapsed years ago. If a demand letter is asserting this patent today, the most potent response may be a § 286 limitations / expiration defense, not an invalidity theory. Note also the internal inconsistency in the bibliographic data: the record lists a 1997-10-31 priority date yet also shows a 1998-01-09 priority claim from JP1514998A — verify the actual earliest priority date against the JP family before relying on any prior-art date calculation.

No pattern signals to exploit. There is no serial petitioner (no repeat filer hammering this patent), no defensive aggregator (Unified Patents / RPX) with a filing in the chain, and no patent-owner PTAB appeal practice to read. Because no IPR was ever instituted, no § 315(e)(2) estoppel has attached to anyone — a defendant is free to raise any § 102/§ 103 ground in district court, and equally free to file a fresh IPR petition, though the expiration date makes the latter largely academic. Silence from the PTAB on a nearly 30-year-old patent that sat in a large, litigious portfolio (Seiko Epson) is itself a signal: this patent was apparently never valuable enough to assert in a way that provoked a validity challenge.

Recommended next steps

• Establish the status first, and lead with it. Confirm the expiration date and legal status on the face of the ODP/Google Patents record: anticipated expiration 2018-10-23, status Expired – Lifetime. If the patent has expired, scour the demand letter for the accused-activity window — a demand premised on current or recent conduct is defective on its face, and the § 286 six-year damages tail has run.
• Do not claim a PTAB win you don't have. There is no FWD and nothing to link to. If a plaintiff or a third party suggests the patent "survived IPRs" or was "invalidated in IPR," that is false — there were no proceedings at all. Ask for the proceeding number; none exists.
• If you nonetheless want an invalidity posture, commission a pre-AIA § 102/§ 103 search against the correct priority date. The claims are directed to a conventional structure (signal lines on a TFT array substrate shielded by a constant-potential conductive line — see the "Definitions" and claim text in the specification), and the closest art will likely be Seiko Epson's own earlier LCD/TFT-array publications. Build the ground yourself; there is no petitioner's work product to borrow.
• Verify the priority chain before you brief anything. The 1997-10-31 vs. 1998-01-09 discrepancy in the bibliographic data matters to the prior-art window, and especially to whether intervening art qualifies.

Sources reviewed: the USPTO ODP structured "PTAB proceedings on file" block (empty); Google Patents US6262702B1 (bibliographic and legal-status data); PTACTS petition repository; CourtListener; and general web search. No PTAB or CAFC document naming US 6,262,702 was located.

I'll research the assignment record for US 6,262,702.

I found a significant lead — a 2024 Seiko Epson assignment to "138 East LCD Advancements Limited." Let me investigate whether it covers US 6,262,702.

Ownership & Assignment Reconstruction — U.S. Patent No. 6,262,702

Scope note / limitation up front. The authoritative full text supplied for this analysis contains the Google Patents "Legal Events" block for US 6,262,702, which lists exactly one assignment event (1999-06-28, inventor → Seiko Epson). I was able to retrieve substantial portfolio-level context about Seiko Epson's later LCD divestitures, but I could not pull the Assignment Center reel/frame numbers, execution dates, or correspondent-of-record data for this specific patent before exhausting my tool budget. Where a field is unknown I say so rather than guess — no reel/frame is fabricated below.

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Inventors

Pattern check — "inventor departure" signal: Not present. There is only one inventor, and he did not depart Seiko Epson. Murade continued filing Seiko Epson-assigned applications (e.g., US 6,627,485; US 2002/0063676; US 6,433,841 with co-inventor Yoneyama) for years after the 1997 priority date. There is no evidence of a fire-sale-triggering inventor exodus.

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Original assignee

• Entity on the issued patent: Seiko Epson Corporation (Tokyo / Suwa, Nagano, Japan).
• Product embodiment: Yes. Seiko Epson was a genuine operating manufacturer of active-matrix TFT LCD panels and LCD projectors during this era; the patent claims shield image-signal lines from high-frequency clock noise in a TFT-array liquid-crystal apparatus (claims 1–2 families, per the specification's "data signal supply means / electrically conductive line" limitations). This is core commercial LCD-panel technology.
• Current status: Operating (Seiko Epson remains a going concern), but it has exited the small/medium TFT-LCD business. Per BOE's IPR filings, Seiko transferred its TFT-LCD operations (including low-temperature polysilicon IP) to Sony at no cost around 2009 and "exited the LCD market." More recently, Seiko Epson has divested portions of its LCD patent portfolio to 138 East LCD Advancements Limited (see the chain signal below). No Seiko Epson bankruptcy is evidenced.

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Assignment timeline

The authoritative source lists one recorded assignment for US 6,262,702 itself:

• Executed date: not determinable / recorded 1999-06-28 — Reel/Frame: not retrieved (this is the gap I could not close; verify at Assignment Center)
  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS INTEREST)
  • Assignor: Masao Murade
  • Assignee: Seiko Epson Corporation
  • Correspondent: Not determinable from retrieved sources. (Lead, not a finding: the prosecuting attorney of record for a Murade/Seiko Epson family member, US 6,433,841, is Oliff & Berridge, PLC — a plausible correspondent, but I cannot confirm it filed this assignment, so I do not assert it.)
  • Context: Standard employee inventor → employer assignment of the original application; a routine prosecution filing, not an acquisition or transfer-to-asserter.

No further assignments are recorded against US 6,262,702. In particular, the Google Patents legal-events block for this patent shows only the 1999 assignment, then grant (2001-07-17) and anticipated expiration (2018-10-23), status "Expired – Lifetime." There is no recorded post-issuance transfer (no security agreement, merger, release, or later LLC transfer) for this patent in the records I could access.

⚠️ Contradiction/uncertainty to flag explicitly: The broader Seiko Epson LCD portfolio was transferred to 138 East LCD Advancements Limited (Ireland) around 2024-03-15. I confirmed that assignment for a sibling patent (US 9,213,207 B2: "ASSIGNMENT OF ASSIGNORS INTEREST; ASSIGNOR:SEIKO EPSON CORPORATION; REEL/FRAME:067131/0001; Effective date: 20240315" → 138 East LCD Advancements Limited, Ireland) and for other Seiko Epson display patents later re-assigned to "138 East Lcd Advancements Limited" (e.g., US 10,769,981; US 11,170,697; US 11,587,495). However, that 2024 transfer is NOT reflected on the US 6,262,702 record — consistent with the fact that '702 had already expired in 2018. I therefore cannot confirm '702 was swept into the 138 East/Longitude portfolio, and the record as supplied indicates it was not.

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Timeline diagram

timeline
    title Ownership of US 6262702
    1997 : Priority date Japan 19971031
    1998 : US application filed 19981023
    1999 : Assigned to Seiko Epson
    2001 : Patent granted 20010717
    2009 : Seiko Epson exits small LCD business
    2018 : Patent expires 20181023

(A 2024 Seiko Epson → 138 East LCD Advancements event is deliberately omitted because it is documented only for sibling patents, not for '702.)

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NPE / troll-pattern signals

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Verdict

Insufficient data — only the original inventor→employer assignment is recorded against this patent.

US 6,262,702's ownership record consists of a single 1999-06-28 assignment from inventor Masao Murade to Seiko Epson Corporation, with no recorded post-issuance transfers; the patent expired 2018-10-23 while still held by Seiko Epson. That is a null NPE result for this patent specifically. I flag, without conflating it with this patent, that Seiko Epson's sibling LCD portfolio was later moved to 138 East LCD Advancements Limited (reel 067131/0001, effective 2024-03-15) and asserted via Longitude Licensing — but that transfer does not appear on the '702 record, so it cannot be attributed here on the evidence retrieved.

Verification links:

• USPTO Assignment Center: https://assignmentcenter.uspto.gov/ (search "6262702")
• Legacy assignment search: https://assignment.uspto.gov/patent/index.html
• Google Patents legal events: https://patents.google.com/patent/US6262702/en

Fields still requiring primary-source confirmation (I could not retrieve them): execution date and reel/frame of the 1999-06-28 Murade→Seiko Epson assignment, and its correspondent of record. If you can pull the Assignment Center abstract for this patent number, I can complete the correspondent/recurrence analysis in signal #3.

I'll search for the specific patent and its prior art citations.

Let me search for the specific citation lists for this patent.

Let me look for the European family member's search report and the patent's citation list specifically.

Search result: US 6,262,702 — confirmation and citation-status

Record confirmed (Google Patents / USPTO-derived data, fetched via search):

Family / related documents located:

• JPH11223832A (JP H11-223832 A), published 1999-08-17, Seiko Epson — Japanese counterpart (titled "Electrooptic device and electronic equipment").
• JP3589005B2 — JP grant corresponding to JP1514998A.
• EP0950917A1 — European counterpart, "Electro-optical device and electronic apparatus"; claims text mirrors the US claims (the EP text quotes "Claims 21 to 23" and an image-signal-line comb arrangement).
• US 6,483,493 B2 — continuation from US 09/828,965 (priority to the present case).

Hard limitation on this answer — please read before relying on it

I was unable to retrieve the "References Cited" (front-page prior-art) list of US 6,262,702 within the available search budget. The full text supplied in the task is truncated and does not include the citation block, and repeated targeted searches of Google Patents / USPTO / Espacenet mirrors returned the specification body, the "Definitions" section, family members, and forward citations — but never the patent's own cited references.

Per the strict rule in the task ("interpret identifiers literally; if you do not know something with high confidence, say so explicitly rather than fabricating"), I will not invent patent numbers or pretend they appear on the face of US 6,262,702. The reference list below is therefore split into (A) what I actually retrieved, and (B) candidate references drawn from a co-cited cluster in the same family/field — explicitly flagged as unverified and not confirmed as laid out on the '702 front page.

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A. References actually retrieved (grounded)

A1. Co-cited cluster appearing alongside US 6,262,702

These appeared in a citation list (from US 7,474,305's "Patent Citations" that includes US 6,262,702). They are co-citations, not confirmed prior art of '702 — but they are the strongest leads because they are same-era, same-field LCD/TFT-array/signal-line-driving documents:

A2. Forward citations (what cites '702 — NOT prior art)

For completeness and to avoid confusion: US 6,262,702 is cited by later documents, e.g. US 7,636,146 B2, US 7,474,305, US 7,193,663 B2, and US 2020/0211445 A1 ("Data driver including noise shielding lines…"). These are later in time and are therefore not § 102 prior art — they only show the patent's technological influence (shielding lines in data drivers).

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B. Candidate prior-art areas to search (clearly unverified)

Because the authoritative front-page list could not be pulled, the honest deliverable is a search plan keyed to the claim limitations, not a fabricated citation list. US 6,262,702 has two independent-claim aspects (matching the EP counterpart's Claim 1 aspect and Claims 21–24):

1. Aspect 1 (Claim 1): TFT array substrate with scanning lines, data lines, switching elements, pixel electrodes; data signal supply means driven in response to a clock signal; an image signal line; a clock signal line; and an electrically conductive line held at a constant potential that shields the image signal line from the clock signal line.
2. Aspect 2 (Claims 21–24): the same matrix, plus a first group and second group of image signal lines routed to opposite sides of the data-signal supply means (comb arrangement).
3. Dependent claims (from the specification's "Definitions" section): constant-potential line = VSSX/VDDX power-supply wiring; positive line surrounds the clock lines and negative line surrounds the image lines (double shielding); the conductive line routed under the light-shielding frame; formed of the same low-resistance metal (e.g., Al) as the data lines in the same plane; capacitance line connected to the shielding line.

Key § 102 target claims: independent Claim 1 and independent Claims 21–24 carry the novel limitations (constant-potential shielding line; two-group comb routing). Dependent claims keyed to VSSX/VDDX lines, "surrounding" geometry, and light-shielding-frame overlap are narrower and easier to design around. If a single reference teaches (i) signal lines carrying image signals and (ii) clock lines on a TFT substrate with (iii) a constant-potential conductor interposed to suppress crosstalk, it anticipates Claim 1. The two-group opposite-side routing in Claims 21–24 is the more likely point of novelty (the specification frames it as solving a "wiring balance"/peripheral-area problem).

Recommended places to look for such § 102 art: Seiko Epson's own 1996–1998 LCD/TFT-array applications (the specification itself cites the applicant's prior JP work), plus contemporaneous Hitachi / Toshiba / Sharp active-matrix and signal-line-driver patents in G02F 1/1362 and G09G 3/36 — i.e., exactly the A1 cluster above, which must be checked limitation-by-limitation.

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C. Required verification steps (to complete this task properly)

To produce the actual per-reference § 102 mapping the task requires, pull the authoritative citation list directly:

1. USPTO Patent Center / Public PAIR for application 09/331,841 — the "References Cited" and "Foreign Patent Documents" tabs give the examiner-cited list (PTO-892).
2. Google Patents → US6262702B1 → "Patent Citations" / "Cited By" tabs (distinct lists; only "Patent Citations" are prior art).
3. Espacenet INPADOC + the EP0950917A1 search report — the ISR/ESR categories (X/Y/A) preserve the examiner's relevance judgments and are the single best proxy for a § 102/§ 103 mapping.
4. Global Dossier for JP3589005 / JPH11223832A to capture JP-cited art.
5. Resolve the priority-date discrepancy (1997-10-31 vs. 1998-01-09 JP1514998A) before dating any reference — it determines whether US 6,377,235 (filed 1997-11-28) is even in the prior-art window.

Bottom line: I confirmed the patent and its family, but I could not retrieve its actual cited-references list within the search budget, so I can neither certify a complete prior-art list nor map any specific reference to specific claims under § 102 as of that list. The A1 cluster (US 6,229,513, US 6,266,039, JPH1165536A) are the most promising unverified candidates — they are same-field, same-era, pre-priority documents that appear co-cited with '702 — but they must be confirmed against the PTO-892/ESR before any § 102 assertion. I have deliberately not fabricated citations for the '702 front page.

I'll research the prior art landscape for this patent before building the obviousness analysis.

Let me dig into the specific prior art cited on the face of this patent and the most relevant neighboring references.

Obviousness Analysis — U.S. Patent 6,262,702 under 35 U.S.C. § 103

0. Scope, framework, and evidentiary caveats (read first)

Legal framework. U.S. 6,262,702 has a §371 national-stage filing date of 1998-10-23 and a documented JP priority claim of 1998-01-09 (JP1514998A / parent JP3589005B2). It is therefore governed by pre-AIA § 103(a). The applicable test is the Graham v. John Deere quartet: (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; and (4) secondary considerations. KSR Int'l v. Teleflex (2007) additionally permits rejection where the combination is of known elements according to known methods to yield predictable results, or is an obvious design choice among a finite set of identified solutions.

Two threshold caveats I must state plainly:

1. I could not retrieve the actual "References Cited" list printed on the face of U.S. 6,262,702. The Google Patents page I reached exposes the specification, "Definitions," and CPC classifications, but the front-page U.S./foreign patent references were not in the retrieved text. The user instruction refers to a "Prior Art section of this page"; if a discrete Prior-Art panel existed, its contents were not in my excerpt. I therefore build the combinations below from (a) references I did surface in search, and (b) the well-established state of the art reflected in the specification's own "Definitions" section. Every reference below should be verified against the printed front page before being relied upon in a brief.

2. The strongest reference I found carries a date risk (discussed in §4). Treat its status as prior art as unconfirmed.

Because the patent is expired (anticipated expiration 2018-10-23), this analysis is defensive/informational; the primary invalidity story remains § 286 + expiration, as the earlier sections concluded. A § 103 analysis is useful only for pre-expiration conduct, portfolio diligence, or family member prosecution.

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1. The claims to be analyzed

Independent claim 1 ("first aspect") — element breakdown

Independent claim 11 ("second aspect") — element breakdown

Key observation for § 103: Element 1.9 and 11.6 are the only elements that distinguish the claims from a conventional active-matrix TFT-LCD built-in-driver architecture. Everything else (1.1–1.8, 11.1–11.4) was undeniably conventional by the 1997 priority date — the specification itself concedes these are "known" ("the conventional technique of supplying a relatively low-frequency data line side reference clock signal to the data line driving circuit"). The inventive contribution, if any, is the architectural placement of a constant-potential conductor as a shield, plus (claim 11) balanced dual-side routing.

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2. Level of ordinary skill in the art (LOSITA)

A POSITA in 1997–98 would be a person with a bachelor's degree in electrical engineering, physics, or materials science and 2–3 years of experience in active-matrix display design, or equivalent. That person would be familiar with: TFT-array substrate layout; peripheral built-in driver circuits (shift registers, sampling circuits, waveform/buffer stages); serial-to-parallel phase expansion of video signals; and the well-known problem of capacitive/inductive crosstalk between high-frequency clock lines and low-level analog video lines. Basic shielding theory (interposing a grounded/constant-potential conductor, increasing line-to-line spacing, orthogonal routing) is textbook-level knowledge for this person.

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3. The state of the art, and what the specification itself admits

The "Definitions" section of US 6,262,702 is effectively an admission of the prior art:

• Scanning lines, data lines, pixel electrodes, TFTs, a data line driving circuit + sampling circuit ("data signal supply means"), and a scanning line driving circuit were all known.
• Multi-phase serial-to-parallel conversion of the image signal was known ("the number of phases into which the original image signal is serial-to-parallel converted is increased, it is possible to reduce the frequency of the image signals supplied to the sampling circuit").
• Clock noise degrading the image signal at high dot frequencies (XGA ≈ 65 MHz, SXGA ≈ 135 MHz) was a known problem, and the spec notes a mere ~10 mV of noise produces visible artifacts in a halftone image.
• The spec expressly characterizes the prior-art routing as: control/clock wirings extending to one side of the data line driving circuit and "many wirings for image signals" extending to the other side, resulting in poor wiring balance.

That last admission is important for claim 11: the patentee concedes that single-side concentration of clock lines opposite image lines was the known baseline. Claim 11's contribution is splitting the image lines onto both sides.

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4. Prior art references identified

Reference A — US 6,281,865 B1, "Liquid crystal display device" (source: https://patentimages.storage.googleapis.com/6d/72/ad/00e1c52b109d6d/US6281865.pdf)

This is the closest reference I found. It discloses an LCD with:

• a first insulating substrate bearing driver TFTs (driving circuit), signal lines, scan lines, pixel TFTs, and clock lines for supplying clock signals to the driver circuit;
• video signal lines ("VID"/video) feeding the driving circuit;
• an explicit statement: "a shield line at a fixed potential is disposed between video signal lines" and "a shield line is inserted between clock lines or video signal lines, so that the mutual interference between clock lines or video signal lines can be suppressed"; and
• claims directed to a shielding line disposed on the interval between the clock lines and shield lines biased at a fixed potential.

This maps squarely onto claim 1 elements 1.2–1.9. Date risk: US 6,281,865 issued 2001-08-28, implying a 1998–99 filing. If its filing date is after the 1998-01-09 JP priority but before the 1998-10-23 US filing, it is at best § 102(e) art contingent on the applicant's invention date, and may not qualify at all. This must be verified before use. Its value is strongest as evidence of the state of the art (i.e., that fixed-potential shield lines between clock and video lines were known), which supports § 103 regardless of whether it is technically § 102 art.

Reference B — US 2007/0045626 A1 (Seiko Epson) (source: https://patentimages.storage.googleapis.com/e7/73/d8/5e38ffd468f731/US20070045626A1.pdf)

Seiko Epson's own later publication describing a built-in-driver TFT LCD in which "the constant-potential wiring line serves as the shielding layer." This post-dates 6,262,702 and is not prior art, but it is powerful evidence of the ordinary-skill baseline: it confirms that using a constant-potential wiring line already present for power supply as the shield was a routine, self-evident extension by the mid-2000s, and it mirrors the very structure of dependent claim 2. Use it to show the claimed "power-supply-line-as-shield" feature was conventional, not to show anticipation.

Reference C — the PTAB petition reference lists (sources: https://ptacts.uspto.gov/ptacts/public-informations/petitions/1550934/... and .../1558427/...)

These petitions (involving a related Seiko Epson electro-optical-device patent — not 6,262,702; see the earlier PTAB section confirming no proceedings on 6,262,702) cite a reference-document list including: JP H11-202367; JP H05-053135; JP H06-011684; JP H10-048663; JP 2000-162634; JP H08-328042; JP H08-146448; JP H04-056828, and a Japanese abstract describing a shield "made of the same film as the data line" shielding a signal line connected to a peripheral circuit. This cluster is in the same technical field and is a productive prior-art hunting ground. None of these dates have been verified here, and H11-202367 / JP 2000-162634 may post-date the priority date. Flag for verification.

Reference D — Family/self references (NOT prior art)

• WO 99/23530 A1 and EP 0 950 917 A1 are the PCT/EP family members of this very application (https://patents.google.com/patent/WO1999023530A1, http://data.epo.org/gpi/EP0950917A4-...). They are the same invention, not prior art, and cannot be combined against the claims.

Reference E — General/knowledge-based evidence

The retrieved excerpt also surfaced the general principle in the LCD-art literature that "electromagnetic waves decay with distance, depending on the presence of an obstacle," and that increasing the number of conductors between an aggressor and victim line reduces coupling — the exact rationale the specification uses. This is judicially noticeable textbook electromagnetics, not a documentary reference.

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5. Combination 1 — Claim 1 is likely obvious

Proposed combination: Reference A (US 6,281,865) alone, or Reference A + the ordinary knowledge evidenced by References B/C.

Claim 1 requires no more than: a conventional active-matrix array (1.1–1.5) + known built-in data driver/sampling circuit responsive to a clock (1.6) + the clock line and the video/image line entering that circuit from external terminals (1.7–1.8) + a fixed-potential conductive line between them (1.9).

Reference A discloses every one of those, including the last: it expressly discloses a "shield line at a fixed potential … between video signal lines" and between clock lines, and its claims recite shield lines "biased at a fixed potential" disposed "on the interval between the clock lines." Placing that same fixed-potential shield between the video/image line and the clock line is not a new invention — it is the same known element (fixed-potential shield) applied to the same known problem (inter-line interference) on the same device, which is the paradigm KSR case of a known technique applied to a known structure yielding a predictable result.

Motivation, articulated:

• The specification and Reference A both identify the same problem: high-frequency clock/video interference degrading the displayed image. A POSITA has an explicit reason to shield.
• The "obstacle" rationale (Reference E / spec's own text) makes the result predictable: a constant-potential conductor between two lines reduces coupling. No unpredictable mechanism is invoked.
• Because the shield can be the existing power-supply wiring (VSSX/VDDX/VSSY/VDDY) (dependent claim 2), the solution adds no terminal and no net wiring — the very "simplification in structure and a reduction in space" the spec touts. Minimal cost + known benefit = strong motivation.

Functional-language caveat: Element 1.9's "for shielding" is functional. Under In re Schreiber, an article claim reciting intended use is not patentable over a structure that inherently performs that function. A constant-potential conductor physically disposed between the image line and clock line inherently shields; the claim adds no structural limitation beyond the conductor's position and potential.

Predicted outcome: Claim 1 would likely be held obvious, subject only to the Reference A date-verification caveat.

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6. Combination 2 — Claim 11 is likely obvious

Claim 11 differs from claim 1 chiefly in element 11.5: the image signal lines are split into two groups routed to opposite sides of the data signal supply means, with a shielding conductor (11.6) covering both groups.

Element 11.1–11.4 are the same conventional array and built-in-driver elements as in claim 1 and are disclosed by Reference A.

Element 11.6 is met by Reference A's fixed-potential shield, which discloses shield lines placed in the routing region generally.

Element 11.5 (the split) is the crux. Here the combination is:

• Reference A or any built-in-driver LCD reference for the array + shield; plus
• a secondary reference or general knowledge showing display signal lines routed to both sides of a driver. Dual-side (left/right) entry of video/source signals to a data driver is a standard layout technique to reduce wiring congestion and balance IR drop and parasitic load. The applicant himself concedes, in the "Definitions" section, that the number of image signal lines grows with the number of serial-to-parallel phases and that concentrating wirings on one side produces "quite bad" wiring balance — an explicit statement of the problem that claim 11 solves.

Motivation, articulated:

• Problem stated by the applicant: unbalanced, one-sided wiring congestion around the data-line driver. Claiming that the fix (spread the lines) is non-obvious is difficult when the patent itself frames balanced distribution as the natural design goal.
• Finite, predictable design choice: a POSITA facing N image lines and a central driver has essentially two options — all on one side, or split across two sides. Choosing the split to gain area for the driver and a larger image display area is a predictable design choice among a small set of identified options, i.e., KSR.
• Claim 11's own dependent refinements (odd/even comb routing; every-two-lines comb routing for 1S inversion) are further layout optimizations that the specification justifies by a known benefit (canceling out common-mode noise between adjacent same-polarity lines; 1S/dot inversion to suppress flicker). Optimizing an arrangement to serve inversion-scheme noise cancellation is routine engineering.

Predicted outcome: Claim 11 would likely be held obvious, provided a specific secondary reference (or a defensible "common knowledge" showing) establishes dual-side signal routing to a display driver in the pre-1998 art. This is the element where the obviousness case is most fact-dependent and where I could not verify a documentary reference — recommend a targeted search of the JP cluster in §4 above (particularly JP H04-056828 and JP H05-053135, both pre-1998) for dual-side/driver-surround routing.

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7. Dependent-claim exposure (§ 103)

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8. Why a POSITA would combine — consolidated motivation

1. Same field, same problem, same solution. Reference A and the challenged patent address the identical problem (clock/video interference in a built-in-driver LCD) and the identical solution (fixed-potential shield between signal lines). KSR; In re Icon Health & Fitness.
2. Predictable result. Shielding by a constant-potential conductor is well-understood electromagnetics with a known, quantifiable benefit. No unexpected result is claimed or demonstrated.
3. Design incentives. Reducing terminal count and wiring space (claim 2), avoiding aperture-ratio loss (claim 7), and minimizing mask/process steps (claims 8–9) are ordinary, recognized engineering objectives.
4. Applicant's own admissions. The "Definitions" section concedes the conventional array, the known multi-phase approach, the known noise problem, and the known one-sided-routing imbalance — each of which supplies the missing motivation for the claimed refinements.
5. Prior-art "obstacle" teaching. The spec's own "electromagnetic waves decay with distance, depending on the presence of an obstacle" is the general-knowledge rationale a POSITA would apply to arrive at every geometry claimed (between-lines, surrounding, opposite-direction routing, under the black mask, terminal ordering).

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9. Limitations, counterarguments, and what would change the conclusion

Where the obviousness case is weakest / most fact-dependent:

• Reference A's date. If US 6,281,865 was filed after 1998-01-09, it may not be § 102 prior art. Its value then drops to evidence of the level of skill / general knowledge (still usable, but weaker). Verify the filing date.
• Element 11.5 (dual-side split). I could not verify a single documentary reference teaching image-signal lines split to both sides of a data-line driver with a shield over both groups, pre-1998. The case here rests on (a) the applicant's own problem admission and (b) KSR design-choice reasoning. A defendant should locate the JP cluster (H04-056828, H05-053135, H06-011684, H08-146448, H08-328042) and search for dual-side source-driver routing.

Likely patentee rebuttals (and their strength):

• "References teach shielding between video lines or between clock lines, not shielding an image line from a clock line." — Weak. Reference A literally says "between clock lines or video signal lines," and the same fixed-potential shield element applied across an adjacent pair is the obvious combination.
• "The specific terminal ordering / comb routing is not taught." — Partially effective for the narrowest dependents, but these are pinout/layout optimizations with stated rationales; hard to sustain non-obviousness.
• Secondary considerations. No evidence in the record of unexpected results; the spec presents benefits as inherent and expected. Commercial success (Seiko Epson LCD projectors) would be attenuated because it is not shown to be coextensive with the shield structure. Any long-felt-need argument is undercut by the routine availability of the technique.

What I did NOT verify and cannot assert:

• The verbatim "References Cited" list on the face of 6,262,702 (see §0).
• The filing dates of US 6,281,865 and of every JP reference in the petition list.
• Whether any single reference anticipates (which I do not assert; this is an obviousness-only analysis).

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10. Bottom line

• Claim 1 is very likely obvious over a fixed-potential shield-line LCD reference (best candidate: US 6,281,865), alone or with general knowledge — the only distinguishing element is a known shielding technique applied, predictably, between the same two line types on the same device.
• Claim 11 is likely obvious as well, on a KSR design-choice theory (balanced dual-side routing to solve the wiring-congestion problem the applicant himself concedes) combined with the same shield reference — but this is the element that most needs a verified secondary reference for dual-side signal routing.
• Dependent claims 2, 7, 8–9 are the most vulnerable to § 103 (power-rail-as-shield, shield-under-black-matrix, same-metal-same-step), with clear, dispositive engineering motivations.
• Because the patent is expired (§ 286 tail long lapsed), this § 103 analysis is a fallback; the controlling defense remains expiration, per the earlier sections. But if a validity position is needed, build the combination around US 6,281,865 + a dual-side-routing reference + a black-matrix/process-step reference, and verify every date against the printed front page and the JP family before filing.

Sources actually reviewed: Google Patents US6262702B1 and US6483493B2 (specification text); https://patentimages.storage.googleapis.com/6d/72/ad/00e1c52b109d6d/US6281865.pdf (US 6,281,865); https://patentimages.storage.googleapis.com/e7/73/d8/5e38ffd468f731/US20070045626A1.pdf (US 2007/0045626, Seiko Epson); PTAB petitions 1550934 and 1558427 reference lists (ptacts.uspto.gov); WO 99/23530 A1 and EP 0 950 917 A4 family records (EPO Global Patent Index). Front-page "References Cited" for US 6,262,702 was not retrievable in this session.