Patent 12154652

Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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To identify the most relevant prior art for US patent 12154652, I will examine the patent citations listed on the Google Patents page for US12154652. For each cited patent, I will provide its full citation, publication/filing date, a brief description, and discuss which claim(s) of US12154652 it potentially anticipates under 35 U.S.C. § 102.

The USPTO provides a Patent Public Search tool to search its database. Prior art consists of publicly available information before the effective filing date of a patent application, including U.S. patents and published patent applications, foreign patents, and scientific literature. The goal of a prior art search is to determine if an invention is novel and non-obvious.

The priority date for US12154652 is July 17, 2012. Therefore, any prior art must have a publication or priority date before this date.

Here are the patent citations listed for US12154652 and an analysis of their potential relevance:

Patent Citations for US12154652:

  • US20050133852A1

    • Full Citation: US20050133852A1 - High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
    • Publication Date: 2005-06-23 (Priority date: 1996-05-24)
    • Brief Description: This patent application describes high-performance embedded semiconductor memory devices, specifically focusing on DRAMs with multiple dimension first-level bit-lines to enhance performance. The abstract mentions the memory cell array being formed in a core region and having at least two dimensions of first-level bit-lines.
    • Potential Anticipation: This reference predates US12154652 and discusses embedded DRAM, which is the broad field of the invention. While it focuses on bit-line architecture for performance, it lays groundwork for the concept of embedded memory. It doesn't specifically address the multiple voltage domains or the application to an embedded display port with specific voltage levels lower than 1.1V for peripheral and I/O units, which are central to claims 1, 2, and 3 of US12154652. However, the concept of an "embedded semiconductor memory device" could be considered relevant to the "DRAM comprised in the DRAM" language in claims 1, 2, and 3.

  • US20090122620A1

    • Full Citation: US20090122620A1 - Systems and Methods for Low Power, High Yield Memory
    • Publication Date: 2009-05-14 (Priority date: 2007-11-08)
    • Brief Description: This patent application describes systems and methods for low power, high yield memory. It particularly focuses on reducing power consumption by controlling supply voltages to different memory components based on performance requirements. For example, it discusses reducing voltage during standby or low-performance modes.
    • Potential Anticipation: This patent is highly relevant as it explicitly addresses low power memory, a primary objective of US12154652. The disclosure of dynamically adjusting supply voltages to memory components for power reduction could potentially anticipate aspects of claims 1, 2, and 3 of US12154652, particularly the concept of operating memory units (core, peripheral, I/O) at different, potentially lower, voltages. While it doesn't specify an "embedded display port" application, the general principle of low-power operation through voltage control is a strong point of overlap. The "third voltage is lower than 1.1V" for the input/output circuit in claims 1, 2, and 3, and the "first voltage is lower than 1.1V" in claims 1, 2, and 4, and "second voltage is lower than 1.1V" in claim 5 are specific voltage limitations that might not be explicitly found in this reference but the underlying motivation for low power through voltage control is present.

  • US20100290300A1

    • Full Citation: US20100290300A1 - Semiconductor integrated device
    • Publication Date: 2010-11-18 (Priority date: 2009-05-14)
    • Brief Description: This patent application describes a semiconductor integrated device that includes a plurality of circuit blocks and a power supply control circuit. It discusses providing different voltages to different circuit blocks, including a memory circuit, for power saving.
    • Potential Anticipation: Similar to US20090122620A1, this reference addresses power saving in semiconductor devices by supplying different voltages to different circuit blocks, including memory. This aligns with the fundamental concept of US12154652 to operate different units (memory core, peripheral, I/O) at distinct and lower voltages to reduce power consumption. This could potentially anticipate aspects of claims 1, 2, and 3, particularly the idea of providing different operating voltages to different parts of the DRAM for power efficiency. The specific voltage thresholds of "lower than 1.1V" for certain units would need to be directly found to be fully anticipatory under 35 U.S.C. § 102.

Other Patent Citations (Less Direct Relevance to Core Claims):

  • US5928336A

    • Full Citation: US5928336A - PC card and peripheral device
    • Publication Date: 1999-07-27 (Filing Date: 1996-07-15)
    • Brief Description: This patent describes a PC card and a peripheral device, focusing on interfaces and connections for such devices.
    • Potential Anticipation: This patent is broadly related to peripheral device interfaces but does not appear to directly address the specific low-voltage DRAM architecture or its application in an embedded display port as claimed in US12154652.

  • US6097070A

    • Full Citation: US6097070A - MOSFET structure and process for low gate induced drain leakage (GILD)
    • Publication Date: 2000-08-01 (Filing Date: 1999-02-16)
    • Brief Description: This patent is concerned with MOSFET structures and processes for reducing gate-induced drain leakage.
    • Potential Anticipation: This patent relates to semiconductor device manufacturing and leakage current reduction, which are fundamental to power consumption. However, it does not describe the architectural features of the DRAM or its application as claimed in US12154652. It might be relevant as background technology but not directly anticipatory of the claims.

  • US6363014B1

    • Full Citation: US6363014B1 - Low column leakage NOR flash array-single cell implementation
    • Publication Date: 2002-03-26 (Filing Date: 2000-10-23)
    • Brief Description: This patent describes a NOR flash array designed for low column leakage.
    • Potential Anticipation: This patent focuses on NOR flash memory, which is a different type of memory than DRAM. While it addresses low leakage (related to power), its specific implementation and memory type differ from the claimed invention.

  • US20030031043A1

    • Full Citation: US20030031043A1 - Integrated dynamic memory, and method for operating the integrated dynamic memory
    • Publication Date: 2003-02-13 (Filing Date: 2001-08-13)
    • Brief Description: This patent application describes an integrated dynamic memory and a method for operating it.
    • Potential Anticipation: This is a general reference to integrated dynamic memory. Without further details on voltage operation or specific architectural divisions for power saving, it is unlikely to directly anticipate the specific claims of US12154652 that define voltage levels for different units.

  • US6551896B2

    • Full Citation: US6551896B2 - Capacitor for analog circuit, and manufacturing method thereof
    • Publication Date: 2003-04-22 (Filing Date: 1999-12-17)
    • Brief Description: This patent describes a capacitor for analog circuits and its manufacturing method.
    • Potential Anticipation: This patent is related to basic circuit components and manufacturing, not directly to the DRAM architecture or power management strategies of US12154652.

  • US6570787B1

    • Full Citation: US6570787B1 - Programming with floating source for low power, low leakage and high density flash memory devices
    • Publication Date: 2003-05-27 (Filing Date: 2002-04-19)
    • Brief Description: This patent describes programming techniques for low power, low leakage, and high-density flash memory devices.
    • Potential Anticipation: This patent focuses on flash memory, which is distinct from DRAM, and its programming methods. While it addresses low power and low leakage, the specific memory technology and the claimed architecture of US12154652 are different.

  • US20050010746A1

    • Full Citation: US20050010746A1 - Method for dynamically building acpi architecture
    • Publication Date: 2005-01-13 (Filing Date: 2003-07-07)
    • Brief Description: This patent application describes a method for dynamically building ACPI (Advanced Configuration and Power Interface) architecture.
    • Potential Anticipation: This relates to power management at a system level (ACPI) rather than the specific internal architecture and voltage regulation of a DRAM for an embedded display port as claimed in US12154652.

  • US20060047985A1

    • Full Citation: US20060047985A1 - Data storage apparatus and control method thereof
    • Publication Date: 2006-03-02 (Filing Date: 2004-08-31)
    • Brief Description: This patent application describes a data storage apparatus and its control method.
    • Potential Anticipation: This is a broad title that likely covers various data storage methods. Without further details, it's difficult to assess direct anticipation of US12154652's specific claims regarding low-voltage DRAM for eDP.

  • US20060120138A1

    • Full Citation: US20060120138A1 - Semiconductor memory with volatile and non-volatile memory cells
    • Publication Date: 2006-06-08 (Filing Date: 2004-10-29)
    • Brief Description: This patent application describes a semiconductor memory device that includes both volatile and non-volatile memory cells.
    • Potential Anticipation: While it deals with semiconductor memory, the combination of volatile and non-volatile cells is not a central feature of US12154652's claims, which focus on low-voltage operation of a DRAM.

  • US20060140004A1

    • Full Citation: US20060140004A1 - Semiconductor device
    • Publication Date: 2006-06-29 (Filing Date: 2000-03-09)
    • Brief Description: This patent application describes a general semiconductor device.
    • Potential Anticipation: This is a very broad reference and unlikely to anticipate the specific architectural and voltage-related claims of US12154652 without more specific details.

  • US20060192282A1

    • Full Citation: US20060192282A1 - Semiconductor device
    • Publication Date: 2006-08-31 (Filing Date: 2005-02-25)
    • Brief Description: This patent application describes a general semiconductor device.
    • Potential Anticipation: Similar to the above, this broad reference is unlikely to directly anticipate the specific claims of US12154652.

  • US20060259679A1

    • Full Citation: US20060259679A1 - Method and system for memory access
    • Publication Date: 2006-11-16 (Filing Date: 2005-05-11)
    • Brief Description: This patent application describes a method and system for memory access.
    • Potential Anticipation: This is a general reference to memory access. It's unlikely to anticipate the specific low-voltage DRAM architecture for eDP as claimed in US12154652.

  • US7295036B1

    • Full Citation: US7295036B1 - Method and system for reducing static leakage current in programmable logic devices
    • Publication Date: 2007-11-13 (Filing Date: 2005-11-30)
    • Brief Description: This patent describes a method and system for reducing static leakage current in programmable logic devices.
    • Potential Anticipation: While addressing leakage current (related to power), this patent focuses on programmable logic devices, which are different from DRAM. Its specific techniques might not directly apply to or anticipate the architectural claims of US12154652.

  • US20080117700A1

    • Full Citation: US20080117700A1 - Dynamic semiconductor storage device and method for operating same
    • Publication Date: 2008-05-22 (Filing Date: 2006-11-20)
    • Brief Description: This patent application describes a dynamic semiconductor storage device and a method for operating it, focusing on improving refresh operations and reducing power consumption during such operations.
    • Potential Anticipation: This reference addresses power consumption in dynamic semiconductor storage devices (like DRAM), particularly concerning refresh. While relevant to power, it might not explicitly disclose the distinct low-voltage operation for memory core, peripheral, and I/O units, and the application to an embedded display port, as precisely defined in US12154652's claims.

  • US20090067217A1

    • Full Citation: US20090067217A1 - Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same
    • Publication Date: 2009-03-12 (Filing Date: 2007-02-27)
    • Brief Description: This patent application describes methods for supplying power supply voltages in semiconductor memory devices. It focuses on generating and supplying appropriate internal voltages based on operating modes to reduce power consumption.
    • Potential Anticipation: This patent is relevant because it deals with supplying power supply voltages in semiconductor memory devices to reduce power consumption. This general concept of differentiated voltage supply for power saving could potentially anticipate the principles behind claims 1, 2, and 3 of US12154652. However, the specific voltage levels ("lower than 1.1V") and the application to an embedded display port would need to be present for direct anticipation.

  • US20100005439A1

    • Full Citation: US20100005439A1 - Designing method of semiconductor integrated circuit
    • Publication Date: 2010-01-07 (Filing Date: 2007-03-27)
    • Brief Description: This patent application describes a designing method for a semiconductor integrated circuit.
    • Potential Anticipation: This is a broad reference to design methods and unlikely to anticipate the specific architectural and voltage-related claims of US12154652.

  • US20100008172A1

    • Full Citation: US20100008172A1 - Dynamic type semiconductor memory device and operation method of the same
    • Publication Date: 2010-01-14 (Filing Date: 2008-07-14)
    • Brief Description: This patent application describes a dynamic type semiconductor memory device and its operation method.
    • Potential Anticipation: Similar to other general memory references, it's unlikely to anticipate the specific low-voltage DRAM architecture for eDP as claimed in US12154652 without more detailed disclosure.

  • US20100074043A1

    • Full Citation: US20100074043A1 - Semiconductor device
    • Publication Date: 2010-03-25 (Filing Date: 2008-09-19)
    • Brief Description: This patent application describes a general semiconductor device.
    • Potential Anticipation: A broad reference, unlikely to anticipate the specific claims of US12154652.

  • US7692979B2

    • Full Citation: US7692979B2 - Memory readout circuit and phase-change memory device
    • Publication Date: 2010-04-06 (Filing Date: 2006-11-21)
    • Brief Description: This patent describes a memory readout circuit and a phase-change memory device.
    • Potential Anticipation: This patent focuses on phase-change memory, a non-volatile memory technology, and its readout circuits, which is distinct from the DRAM technology of US12154652.

  • US20100095137A1

    • Full Citation: US20100095137A1 - Dynamic Frequency And Voltage Scaling For A Computer Processor
    • Publication Date: 2010-04-15 (Filing Date: 2008-10-13)
    • Brief Description: This patent application describes dynamic frequency and voltage scaling for a computer processor.
    • Potential Anticipation: This reference is related to power management at the processor level using dynamic voltage and frequency scaling. While it involves voltage control for power saving, it's applied to a processor, not specifically the internal architecture and distinct voltage domains of a DRAM as claimed in US12154652.

  • US7894294B2

    • Full Citation: US7894294B2 - Operational mode control in serial-connected memory based on identifier
    • Publication Date: 2011-02-22 (Filing Date: 2008-01-23)
    • Brief Description: This patent describes controlling operational modes in serial-connected memory based on an identifier.
    • Potential Anticipation: This patent focuses on operational modes and identifiers for serial-connected memory, not the specific low-voltage DRAM architecture or its application in an embedded display port as claimed in US12154652.

  • US20110069562A1

    • Full Citation: US20110069562A1 - Low consumption voltage regulator for a high voltage charge pump, voltage regulation method, and memory device provided with the voltage regulator
    • Publication Date: 2011-03-24 (Filing Date: 2009-09-18)
    • Brief Description: This patent application describes a low-consumption voltage regulator for a high-voltage charge pump, a voltage regulation method, and a memory device using it.
    • Potential Anticipation: This reference is relevant to voltage regulation and low consumption in memory devices. It could be considered relevant to the "peripheral circuit unit" which often includes voltage generation/regulation, and therefore could be broadly relevant to the power-saving aspects of US12154652, especially claims involving a peripheral circuit unit operating at a low voltage.

  • TW201123198A

    • Full Citation: TW201123198A - Memory power supply circuit
    • Publication Date: 2011-07-01 (Filing Date: 2009-12-18)
    • Brief Description: This Taiwanese patent application describes a memory power supply circuit.
    • Potential Anticipation: As a memory power supply circuit, it directly addresses power delivery to memory. Depending on the specifics of its voltage output levels and how it supplies different memory components, it could potentially anticipate the low-voltage operation aspects of US12154652's claims. Without the full text, a precise assessment is difficult.

  • CN102187323A

    • Full Citation: CN102187323A - Dynamic utilization of power-down modes in multi-core memory modules
    • Publication Date: 2011-09-14 (Filing Date: 2008-08-13)
    • Brief Description: This Chinese patent application describes dynamic utilization of power-down modes in multi-core memory modules.
    • Potential Anticipation: This reference is relevant to power saving in memory, specifically through power-down modes. While not directly about distinct voltage domains for active operation as in US12154652, the broader goal of reducing power consumption in memory modules is shared.

  • US20110252253A1

    • Full Citation: US20110252253A1 - Energy saving circuit of motherboard
    • Publication Date: 2011-10-13 (Filing Date: 2010-04-09)
    • Brief Description: This patent application describes an energy-saving circuit of a motherboard.
    • Potential Anticipation: This relates to system-level energy saving on a motherboard, not the internal architecture and voltage regulation of a DRAM as claimed in US12154652.

  • US20110292448A1

    • Full Citation: US20110292448A1 - Program execution control method
    • Publication Date: 2011-12-01 (Filing Date: 2010-05-28)
    • Brief Description: This patent application describes a program execution control method.
    • Potential Anticipation: This reference is to a software-related control method and is unlikely to anticipate the hardware architecture of US12154652.

  • US20120182076A1

    • Full Citation: US20120182076A1 - Limiter circuit and voltage controlled oscillator including the same
    • Publication Date: 2012-07-19 (Filing Date: 2011-01-14)
    • Brief Description: This patent application describes a limiter circuit and a voltage-controlled oscillator.
    • Potential Anticipation: This is a basic circuit design reference and is unlikely to anticipate the specific low-voltage DRAM architecture for eDP as claimed in US12154652. Note that its publication date is after the priority date of US12154652 (July 17, 2012) if the provisional applications are considered, but before the June 19, 2013 filing date of the parent application US13/922,242. If the effective priority date of US12154652 is considered to be the provisional application date of July 17, 2012, then this reference would not be prior art under 35 U.S.C. § 102.

  • US20130046941A1

    • Full Citation: US20130046941A1 - Write circuit, read circuit, memory buffer and memory module
    • Publication Date: 2013-02-21 (Filing Date: 2011-07-11)
    • Brief Description: This patent application describes write circuits, read circuits, memory buffers, and memory modules.
    • Potential Anticipation: This reference describes memory circuits and modules. Since its publication date is after the priority date of US12154652 (July 17, 2012), it would not be considered prior art for US12154652 under 35 U.S.C. § 102, assuming the priority date relates to the content of the claims.

  • US20130132660A1

    • Full Citation: US20130132660A1 - Data read/write system
    • Publication Date: 2013-05-23 (Filing Date: 2011-07-11)
    • Brief Description: This patent application describes a data read/write system.
    • Potential Anticipation: Similar to US20130046941A1, its publication date is after the priority date of US12154652 (July 17, 2012). Thus, it would not be considered prior art for US12154652 under 35 U.S.C. § 102, assuming the priority date relates to the content of the claims.

  • US20130135955A1

    • Full Citation: US20130135955A1 - Memory device including a retention voltage resistor
    • Publication Date: 2013-05-30 (Filing Date: 2011-11-29)
    • Brief Description: This patent application describes a memory device including a retention voltage resistor.
    • Potential Anticipation: Its publication date is after the priority date of US12154652 (July 17, 2012). Thus, it would not be considered prior art for US12154652 under 35 U.S.C. § 102, assuming the priority date relates to the content of the claims.

Family Cites Families:

  • TWM276302U

    • Full Citation: TWM276302U - DRAM of a 3-transistor cell
    • Publication Date: 2005-09-21 (Priority Date: 2005-04-08)
    • Brief Description: This Taiwanese utility model describes a DRAM with a 3-transistor cell.
    • Potential Anticipation: This reference describes a specific DRAM cell architecture. While it is a type of DRAM, it does not appear to directly disclose the multiple voltage domains for power saving or the application to an embedded display port as claimed in US12154652.

  • TWI355590B

    • Full Citation: TWI355590B - Common module for DDRI SDRAM and DDRIII SDRAM
    • Publication Date: 2012-01-01 (Priority Date: 2007-05-15)
    • Brief Description: This Taiwanese patent describes a common module for DDR1 SDRAM and DDR3 SDRAM, allowing for compatibility.
    • Potential Anticipation: This patent focuses on compatibility between different DDR generations of SDRAM. While it mentions DDR I and DDR III specifications, which are also mentioned in US12154652 as compatible modes, it doesn't appear to directly address the low-voltage operation for distinct internal units or the specific application in an embedded display port as the primary inventive features of US12154652's claims.

Most Relevant Prior Art:

Based on the descriptions, the most relevant prior art documents appear to be those that broadly address power reduction in memory by controlling supply voltages to different components:

  1. US20090122620A1 (Systems and Methods for Low Power, High Yield Memory): This reference directly addresses low power memory and controlling supply voltages to different memory components. This aligns strongly with the core concept of US12154652, particularly claims 1, 2, and 3, which specify distinct voltage operations for the memory core, peripheral, and I/O units to reduce power consumption.
  2. US20100290300A1 (Semiconductor integrated device): This patent also focuses on power saving in semiconductor devices, including memory, by providing different voltages to different circuit blocks. This further supports the idea of varying operating voltages within a memory device for power efficiency, which is central to claims 1, 2, and 3 of US12154652.
  3. US20090067217A1 (Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same): This reference is also highly relevant due to its focus on methods for supplying power supply voltages to semiconductor memory devices to reduce power consumption. This directly relates to the voltage control aspects in claims 1, 2, and 3.

These three patents (US20090122620A1, US20100290300A1, and US20090067217A1) lay the foundational concept of power reduction in memory through differential voltage supply, which is a key element of US12154652. While US12154652 adds specific voltage thresholds and the application to an embedded display port, these prior art documents could be used to argue obviousness under 35 U.S.C. § 103, or potentially anticipate if more specific disclosures regarding voltage levels and partitions are found within their full texts. For direct anticipation under 35 U.S.C. § 102, a prior art reference must disclose every element of the claimed invention. Without a detailed analysis of the full text of these references against each claim, it's challenging to definitively state anticipation. However, the core concept of low-voltage operation for different memory sections for power saving is strongly present.

Generated 5/29/2026, 12:49:17 AM