Obviousness — US Patent 12154652

Obviousness Analysis of US12154652 Under 35 U.S.C. § 103

This analysis identifies combinations of prior art references that would render the claims of US patent 12154652 obvious to a person having ordinary skill in the art (PHOSITA). The PHOSITA in this field would be an electrical engineer or memory designer with knowledge of Dynamic Random Access Memory (DRAM) architecture, power management techniques, and display interface standards. The primary motivation for combining these references would be to address the known problem of reducing power consumption in DRAMs, particularly when used as frame buffers for embedded display ports (eDP) with Panel Self Refresh (PSR) functionality, as explicitly outlined in the background of US12154652 itself.

Background and Motivation for a PHOSITA

The background section of US12154652 establishes that embedded display port (eDP) version 1.3, with its Panel Self Refresh (PSR) function, significantly reduces the power consumption of a Graphics Processing Unit (GPU). However, a timing controller supporting the PSR function requires a frame buffer, typically a DRAM, which can increase the timing controller's power consumption. The patent explicitly states that the operation voltages specified by the Joint Electron Device Engineering Council (JEDEC) for standard DDR and low-power DDR specifications (e.g., 1.8V, 2.5V, 3.3V) "can not satisfy requirements... of the embedded display port (eDP) version 1.3." This creates a clear motivation for memory manufacturers to design a frame buffer (DRAM) that significantly reduces the power consumption of the timing controller, necessitating low operation and standby power consumption for the DRAM. Lowering operating voltages is a well-known and conventional approach to reduce power consumption in semiconductor devices.

Combinations of Prior Art References and Obviousness Arguments

The following prior art references, individually or in combination, teach or render obvious the elements of the independent claims of US12154652.

Prior Art References Utilized:

US20030031043A1 to Pochmuller ("Integrated dynamic memory, and method for operating the integrated dynamic memory"): This patent teaches an integrated dynamic memory with memory cells and peripheral circuits, featuring a memory-cell voltage generator and a peripheral voltage generator. Crucially, it discloses that in a low-power mode, the memory-cell voltage (equivalent to the DRAM core cell voltage) is reduced to a value below 1V.
US20090122620A1 to Qualcomm Incorporated ("Systems and Methods for Low Power, High Yield Memory"): This reference describes a memory device including a memory array (core) and an interface circuit (input/output) that operate at a "reduced voltage relative to a standard operating voltage" for low power.
US20090067217A1 to [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) ("Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same"): This patent teaches a semiconductor memory device where a cell array (core) is supplied with a first voltage, and a peripheral circuit is supplied with a second voltage. It explicitly states that "The first voltage is less than the internal voltage" (where internal voltage is the second voltage for the peripheral circuit), demonstrating the use of different voltages for different DRAM units.
Iyer, S.S. and Kalter, H.L., "Embedded DRAM technology: opportunities and challenges" (1999): This non-patent literature discusses "Embedded DRAM technology," confirming the concept of integrating DRAM components onto a single chip with other logic.

Obviousness of Independent Claim 1:

Claim 1 describes a DRAM comprising a DRAM core cell operating at a first voltage lower than 1.1V and an input/output circuit operating at a third voltage also lower than 1.1V. Both are on a single chip, the I/O circuit is external to the core cell, and the first voltage is different from the third voltage.

DRAM core cell (volatile memory cell) supplied with a first voltage lower than 1.1V: Pochmuller teaches an integrated dynamic memory where, in a low-power mode, the memory-cell voltage (equivalent to the DRAM core cell voltage) is reduced to a value below 1V. The volatile nature of a DRAM cell is inherent and well-known in the prior art.
Input/output circuit electrically connected to the DRAM core cell, supplied with a third voltage lower than 1.1V: Qualcomm teaches an "interface circuit" (analogous to an input/output circuit) operating at a "reduced voltage relative to a standard operating voltage" for low power. Given Pochmuller's teaching of a sub-1V core voltage and the explicit motivation in US12154652's background to achieve significant power reduction for eDP applications (which JEDEC standard voltages cannot meet), a PHOSITA would be motivated to reduce the I/O circuit's operating voltage to below 1.1V. The electrical connection between core and I/O is a fundamental aspect of DRAM architecture.
DRAM core cell and the input/output circuit formed on a single chip, the input/output circuit is external to the DRAM core cell: Pochmuller discloses an "integrated dynamic memory." Iyer et al. discuss "embedded DRAM technology." These references establish the prior art concept of integrating DRAM components on a single chip. It is a conventional architectural arrangement for an input/output circuit to be physically external to the memory core cell array but integrated on the same semiconductor chip.
The first voltage is different from the third voltage: Samsung explicitly teaches supplying a cell array (core) with a first voltage and a peripheral circuit with a second voltage, where these voltages can be different (e.g., first voltage less than internal/second voltage). Pochmuller also supports this by describing separate voltage generators for the memory cell and peripheral circuits. Therefore, using different voltages for the core and I/O circuits would be an obvious design choice for a PHOSITA.

Motivation for Combination: A PHOSITA, seeking to reduce power consumption in a DRAM for an eDP application (as motivated by US12154652's background), would combine the low-voltage core operation of Pochmuller with the low-voltage interface operation of Qualcomm. The desire for optimal power savings would lead the PHOSITA to set both voltages below a conventional threshold like 1.1V, recognizing that standard JEDEC voltages are insufficient for the eDP 1.3 PSR requirements. The integration on a single chip and differential voltages are well-established architectural and power management techniques shown in Iyer et al., Pochmuller, and Samsung.

Obviousness of Independent Claim 2:

Claim 2 is similar to Claim 1 but specifies that the first voltage (for the core cell) is greater than the third voltage (for the input/output circuit).

All elements of Claim 1, except for the voltage relationship: As established above, the elements of Claim 1 are obvious.
The first voltage is greater than the third voltage: While Samsung teaches a core voltage less than a peripheral voltage, the patent US12154652 itself, in its detailed description (specifically Table III), illustrates an embodiment where the memory core unit (first predetermined voltage) operates at 1.8V±0.1V while the peripheral circuit unit and input/output unit (second and third predetermined voltages) operate at less than 1.1V. The patent explains that this configuration provides "higher charge pump efficiency" for the memory core unit, while still achieving lower access and input/output power consumption. A PHOSITA, aiming for overall power reduction and efficiency in an eDP application, would be motivated to adopt such a differential voltage scheme, recognizing that maintaining a slightly higher core voltage could optimize certain internal operations (like charge pump efficiency) without sacrificing the significant power savings achieved by operating peripheral and I/O units at very low voltages (e.g., <1.1V).

Motivation for Combination: The motivation remains power reduction for eDP applications. The specific voltage relationship (core voltage > I/O voltage) is explicitly disclosed as a viable and beneficial design choice within the patent's own description (Table III) to optimize efficiency, and would be obvious to a PHOSITA implementing low-power DRAMs.

Obviousness of Independent Claim 3:

Claim 3 describes a DRAM with a DRAM core cell and an input/output circuit, where the input/output circuit operates at a third voltage lower than 1.1V, the first voltage (core) is greater than the third voltage, and the DRAM is capable of being applied to an embedded display port (eDP).

DRAM core cell (volatile memory cell) and input/output circuit supplied with a third voltage lower than 1.1V: As established for Claim 1, this is rendered obvious by Pochmuller's sub-1V core and Qualcomm's reduced-voltage interface circuits, combined with the motivation for significant power reduction in eDP.
The first voltage is greater than the third voltage: As established for Claim 2, this specific voltage relationship, offering benefits like "higher charge pump efficiency" while still achieving overall power reduction, is taught by US12154652's own description (Table III).
The DRAM is capable to be applied to an embedded display port (eDP): The background section of US12154652 extensively details the use of DRAM as a frame buffer for a timing controller in a liquid crystal display with an eDP and PSR function. The entire problem statement and motivation for the patent revolve around adapting DRAM for this specific application to achieve power savings. It would therefore be obvious to a PHOSITA to apply known low-power DRAM techniques, including the specified low-voltage operations, to a DRAM intended for an eDP.

Motivation for Combination: The fundamental motivation is to overcome the power consumption challenges of DRAMs when used as frame buffers in eDP 1.3 PSR systems. The PHOSITA would combine the known architectural elements of DRAM, the established need for extremely low power in eDP contexts (from US12154652's background), and the teachings of low/differential voltage operations from Pochmuller, Qualcomm, and Samsung, to arrive at a DRAM capable of meeting the power efficiency demands of an eDP.

Obviousness of Dependent Claim 4:

Claim 4 depends on Claim 3 and states, "wherein the first voltage is lower than 1.1V."

First voltage (core) lower than 1.1V: This is directly taught by Pochmuller, which discloses a memory-cell voltage (core voltage) reduced to a value below 1V in a low-power mode for an integrated dynamic memory.

Motivation for Combination: As an alternative to a higher core voltage (as in Claim 3), a PHOSITA would be motivated by the overarching goal of power reduction to implement a core voltage below 1.1V, as taught by Pochmuller, particularly when designing for applications like eDP that demand minimal power consumption.

Obviousness of Dependent Claim 5:

Claim 5 depends on Claim 3 and adds "a peripheral circuit comprised in the DRAM, wherein the peripheral circuit is electrically connected to the DRAM core cell, and the peripheral circuit is supplied with a second voltage to make the peripheral circuit operate at the second voltage, wherein the second voltage is lower than 1.1V."

Peripheral circuit in DRAM, electrically connected to core cell: Pochmuller teaches an integrated dynamic memory with "peripheral circuits" and a "peripheral voltage generator." The electrical connection between peripheral circuits and the core cell is standard DRAM architecture.
Peripheral circuit supplied with a second voltage lower than 1.1V: Qualcomm teaches "core driver circuit" (analogous to a peripheral circuit) operating at a "reduced voltage relative to a standard operating voltage" for low power. Given the strong motivation from US12154652's background to significantly reduce power consumption for eDP, and the practice of lowering voltages for power savings, a PHOSITA would find it obvious to apply a voltage below 1.1V to the peripheral circuit, similar to the I/O circuit, to achieve the desired power efficiency.

Motivation for Combination: The motivation to reduce power consumption of the DRAM in eDP applications would drive a PHOSITA to apply low-voltage operation to all relevant functional units, including the peripheral circuits, using known techniques as taught by Pochmuller (peripheral circuits and generators) and Qualcomm (reduced voltage for core drivers).

Obviousness of Dependent Claim 6:

Claim 6 depends on Claim 5 and states, "wherein the first voltage is different from the second voltage."

First voltage (core) is different from the second voltage (peripheral): Samsung explicitly teaches a semiconductor memory device where the cell array (core) is supplied with a first voltage and the peripheral circuit is supplied with a second voltage, stating that "The first voltage is less than the internal voltage" (which is the second voltage for the peripheral circuit). Pochmuller also supports this with separate voltage generators for memory cells and peripheral circuits, enabling different operating voltages.

Motivation for Combination: A PHOSITA would be motivated to use different voltages for the core and peripheral circuits to optimize power consumption and performance characteristics of each unit, as demonstrated by Samsung and Pochmuller. This allows for tailored voltage scaling for different parts of the DRAM, a common power management strategy.

Conclusion

The claims of US12154652 are rendered obvious by combining the identified prior art references. The background of US12154652 itself establishes the clear motivation for a PHOSITA to reduce DRAM power consumption for eDP applications, recognizing the inadequacy of standard JEDEC voltages. The prior art teaches the fundamental components of DRAM (core, peripheral, I/O), their integration on a single chip, and various techniques for operating them at reduced or differential voltages, including sub-1V for the core. A PHOSITA would have been motivated to combine these known techniques and architectural elements in a DRAM designed for an eDP to achieve the desired low-power operation, with the specific voltage thresholds (e.g., <1.1V) being a matter of routine optimization in pursuit of the stated goal of significantly reduced power consumption.