Prior art

To identify the most relevant prior art for US patent 11894306, I will examine the patent citations listed within the patent document itself. The USPTO's Patent Public Search tool is the primary resource for this.

Here's an explanation of anticipation under 35 U.S.C. § 102:
A patent claim is anticipated (and thus not novel) if every element of the claimed invention is identically disclosed, either expressly or inherently, in a single prior art reference. These elements must be arranged as in the claim under review. If there are differences between the reference and the claim, the rejection would typically be based on 35 U.S.C. § 103 (obviousness), which allows for the consideration of multiple references or obvious variations.

Since I do not have direct access to the USPTO database to pull the full list of forward and backward citations, I will analyze the "Prior art keywords" and "Priority date" information available in the provided patent text to infer relevant prior art types, and then explain how one would proceed if direct database access were available.

Prior Art Keywords from US11894306B2:

• metal
• layer
• semiconductor chip
• region
• micrometers

Priority Date: 2012-09-26

These keywords suggest that relevant prior art would involve semiconductor packaging, specifically concerning metal layers, the dimensions of features (micrometers), and various components within a chip package. The priority date is crucial as any anticipating prior art must predate it.

Process for Identifying Most Relevant Prior Art (if direct database access were available):

1. Access USPTO Patent Public Search: I would use the "Patent Public Search" tool provided by the USPTO.
2. Search for US11894306B2: I would enter the patent number 11894306 into the search interface.
3. Identify Cited References (Backward Citations): Once the patent document is retrieved, I would navigate to the "References Cited" section. This section lists all prior art documents (patents, publications, etc.) that were considered by the patent examiner during the prosecution of US11894306. These are often the most directly relevant prior art identified by the USPTO.
4. Identify Citing References (Forward Citations): I would also look for "Cited By" or "Forward Citations" sections if available in the search interface. These are patents that have cited US11894306 as prior art, which can sometimes indirectly point to related earlier inventions.
5. Extract Information for Each Citation: For each identified prior art reference, I would extract:
   • Full citation (e.g., patent number, inventor, title, issue date/publication date).
   • Publication/Filing Date: Crucial for determining if it is indeed "prior" art according to 35 U.S.C. § 102.
   • Brief Description: A summary of the invention disclosed in the prior art.
   • Potential Anticipated Claim(s) under 35 U.S.C. § 102: This requires a detailed comparison of each element of the claims of US11894306 against the entire disclosure of the prior art reference. For a claim to be anticipated, every single element of that claim must be found, either expressly or inherently described, in a single prior art reference, and arranged as in the claim.

Since I cannot perform a live database search, I will describe the type of prior art that would be highly relevant based on the patent's content and general knowledge of semiconductor packaging.

Given the patent's title "Chip package" and its detailed description of forming glass substrates with metal plugs, dielectric layers, metal layers, and connecting various chips (memory, CPU, GPU, etc.) and passive devices, the most relevant prior art would likely include:

• Glass Interposer Technology: Patents describing methods for manufacturing glass substrates with through-glass vias (TGVs) or similar vertical interconnections.
• Redistribution Layers (RDLs): Prior art detailing the fabrication of multi-layered metal and dielectric interconnect structures on substrates, particularly for semiconductor packaging.
• Flip-Chip and Wire Bonding Techniques: Patents related to methods of attaching semiconductor chips to substrates using solder bumps (flip-chip) or metal wires, and the associated pad structures.
• Damascene and Embossing Processes for Metallization: Prior art describing these specific techniques for creating metal traces and layers in microelectronic devices.
• Display Panel Integration: Given the applications in OLED, MEMS, and LCD display substrates, prior art in integrating chip packages with various display technologies would be highly relevant.

Without the specific list of cited prior art from the USPTO database for patent 11894306, I cannot provide the exact citations and their direct anticipation of claims. However, the above categories represent the most likely areas where anticipating prior art would be found, and a full analysis would proceed by comparing the elements of US11894306's claims to the disclosures of such prior art documents.