Obviousness

Obviousness Analysis of US Patent 11894306 under 35 U.S.C. § 103

A person having ordinary skill in the art (POSA) in semiconductor packaging around September 26, 2012 (the priority date of US11894306) would typically possess a bachelor's degree in electrical engineering, materials science, or a related field, along with several years of experience in semiconductor manufacturing, packaging, or display technology. This individual would be familiar with various packaging techniques (e.g., flip-chip, wire bonding), interconnect technologies (e.g., bumps, vias, redistribution layers), and substrate materials (e.g., silicon, glass, organic). The prevailing motivations in the field at that time included achieving higher integration density, improving electrical performance, enhancing reliability, and reducing manufacturing costs for advanced semiconductor packages and display devices.

The following analysis identifies combinations of prior art references that would render the independent claims of US Patent 11894306 obvious to a POSA.

Independent Claim 1 Analysis

Claim 1: A chip package comprising a glass substrate with through-glass metal plugs, a semiconductor chip attached to its top surface via metal bumps, redistribution layers (RDLs) on the glass substrate (consisting of at least two metal layers and at least two dielectric layers with openings exposing metal), and an underfill layer between the chip and the RDLs.

Prior Art Combination: A POSA would have been motivated to combine the teachings of Corning et al. ("Glass Interposer Substrates: Fabrication, Characterization and Modeling"), WO2012125481A2 ("Thin film through-glass via and methods for forming same"), and Li et al. ("Redistribution Layers (RDLs) for 2.5D/3D IC Integration"), along with general knowledge of flip-chip bonding and underfill.

Rationale for Obviousness:

1. Glass Substrate with Through-Glass Metal Plugs: The use of glass as an interposer for 2.5D/3D applications was well-known, offering advantages like high electrical resistivity, low dielectric constant, low electrical loss, and a tailorable coefficient of thermal expansion (CTE) matching silicon. The concept of through-glass vias (TGVs) as vertical interconnects in glass interposers was also established, with various methods for their formation (e.g., etching, filling with conductive material) being actively developed to overcome manufacturing challenges. Therefore, a POSA would naturally employ a glass substrate with conductive material filled TGVs (metal plugs) for an advanced chip package.
2. Redistribution Layers (RDLs) on Glass Substrate: RDLs were recognized as an integral part of 2.5D/3D IC integration for circuitry fan-out and lateral communication between chips. Prior art detailed RDL fabrication using multiple polymer (dielectric) layers and electroplated copper (metal) layers, with openings for connections. The smooth surface of glass made it particularly suitable for RDL wiring. It would have been obvious to apply these known RDL structures to a glass interposer to facilitate chip connections.
3. Semiconductor Chip Attachment with Metal Bumps and Underfill: Flip-chip bonding, involving metal bumps on a semiconductor chip connected to a substrate, was a standard high-density interconnection method. The use of an underfill layer between the flip-chip and the substrate to enhance mechanical reliability and manage thermal stresses was also a well-established practice in semiconductor packaging.

A POSA, driven by the need for miniaturization, improved electrical performance, and cost reduction in advanced packaging, would find it obvious to combine these known elements to create a chip package as described in Claim 1.

Independent Claim 11 Analysis

Claim 11: A display device comprising a display panel substrate with contact pads and a display area having edges within 100 micrometers of the boundaries, and a glass substrate with metal conductors (TGVs) and metal bumps connecting to the display panel's contact pads.

Prior Art Combination: This claim would be rendered obvious by combining the general knowledge of display panel substrates (e.g., LCDs and OLEDs as described in US8102487B2 and US20090134528A1), the use of glass interposers with TGVs (Corning et al.), and the industry-wide motivation for display miniaturization.

Rationale for Obviousness:

1. Display Panel Substrate with Narrow Borders: Display devices with defined display areas and contact pads were conventional. The continuous industry push for smaller bezels and increased screen-to-body ratios in display devices would motivate a POSA to reduce the distance between the display area edges and the panel boundaries to less than 100 micrometers.
2. Glass Substrate with Metal Conductors (TGVs) and Metal Bumps: Given the established advantages of glass interposers with TGVs for compact routing and signal integrity, a POSA would recognize their applicability for interconnecting components in a display device. Using metal bumps for attachment and electrical connection is a known technique in semiconductor packaging and adaptable to display applications.

It would be an obvious design choice for a POSA, aiming for more compact and high-performance display modules, to use a TGV-enabled glass interposer to connect to the contact pads of a display panel, while simultaneously pursuing the known trend of reducing the display's border dimensions.

Independent Claim 12 Analysis

Claim 12: A display device comprising a display panel substrate with transparent electrodes, a first substrate (glass) with metal plugs (TGVs), and metal bumps connecting the metal plugs to the transparent electrodes through an anisotropic conductive film (ACF) layer containing conductive particles.

Prior Art Combination: This claim would be obvious in light of prior art disclosing glass interposers with TGVs (Corning et al.), display panels with transparent electrodes (US8102487B2), and the well-known technology of anisotropic conductive films (ACF) for electrical connections in displays.

Rationale for Obviousness:

1. Glass Substrate with Metal Plugs: As established, glass substrates with TGVs were known and their benefits for interposers were understood.
2. Display Panel with Transparent Electrodes: Transparent electrodes are a fundamental component of various display technologies, including LCD, OLED, and MEMS displays.
3. ACF Connection: Anisotropic conductive film (ACF) bonding, which uses conductive particles to create electrical connections between components, was a widely adopted and reliable method for connecting driver ICs to display panels (e.g., chip-on-glass, COG) for fine-pitch interconnections in the display industry. The patent itself mentions ACF layer 116 with conductive particles 117 (e.g., Ni, Au, Ag) in the context of connecting metal bumps to transparent electrodes for OLED, MEMS, and LCD displays, implicitly acknowledging its prior art status.

A POSA, seeking reliable and fine-pitch interconnections for integrating a glass interposer with TGVs into a display device, would find it obvious to employ the well-known ACF bonding technology to connect the metal plugs to the transparent electrodes. This combination leverages existing solutions for improved display module integration.

Independent Claim 13 Analysis

Claim 13: A display device comprising a display panel substrate with transparent electrodes on its bottom surface and internal metal plugs connected to them, a first substrate (glass) with metal plugs (TGVs), and metal bumps connecting the metal plugs of the two substrates through a solder layer.

Prior Art Combination: This claim is rendered obvious by combining the use of glass interposers with TGVs (Corning et al.), the concept of through-substrate interconnects (even if in silicon initially, like TSVs, then adapted to glass display panels), and the pervasive use of solder layers for interconnections in flip-chip and other packaging contexts.

Rationale for Obviousness:

1. Glass Substrates with Metal Plugs (TGVs): The existence and benefits of glass substrates with TGVs for advanced packaging were well-established.
2. Through-Substrate Interconnects in Display Panels: While specific prior art for metal plugs within a display panel substrate (connected to transparent electrodes) might not be explicitly detailed, the concept of through-substrate vias was broadly known (e.g., TSVs, TGVs in interposers). A POSA would find it an obvious design choice to extend this known vertical interconnect technology into the display panel itself to achieve more compact and efficient routing for high-density displays.
3. Solder Layer Interconnection: Solder has been a fundamental material for creating robust electrical and mechanical connections between components, particularly in flip-chip bonding, which the patent also references.

A POSA aiming for highly integrated and high-performance display devices would logically combine glass interposers with TGVs with similarly advanced display panels that incorporate internal vertical interconnects. The use of a solder layer for connection between these two TGV-enabled substrates represents a straightforward application of a known and reliable interconnection method.

Independent Claim 14 Analysis

Claim 14: A display device comprising a first substrate (glass) with metal plugs (TGVs), a second glass substrate, and an OLED layer, TFT circuit layers, and transparent electrodes all situated between the first and second glass substrates, where the metal plugs in the first substrate are connected to the transparent electrodes through a first metal layer.

Prior Art Combination: This claim is obvious when considering the known architecture of OLED displays with TFT circuits and transparent electrodes on glass substrates (US20180301513A1, US20160343791A1, "CDT announces Key New Patents Allowed in Printable OLED Display Technology"), combined with the established technology of glass interposers having TGVs (Corning et al.) and general metallization techniques.

Rationale for Obviousness:

1. OLED, TFT, and Transparent Electrodes on Glass Substrates: OLED display devices incorporating organic light-emitting layers, thin-film transistor (TFT) circuit layers, and transparent electrodes on glass substrates were well-developed and commonly known prior to 2012. These are core components of active-matrix OLED (AMOLED) displays.
2. Glass Substrate with Metal Plugs (TGVs): The advantages of glass substrates as interposers with TGVs (e.g., electrical performance, CTE match, potential for thinness) were understood.
3. Integration of TGV-enabled Glass Substrate into Display Stack: A POSA, striving for more integrated and compact display designs, would find it obvious to integrate a TGV-enabled glass substrate directly into the display stack. This provides efficient vertical routing for the TFT circuits and connections to the transparent electrodes within the display module, utilizing a known "first metal layer" for this electrical connection. This approach leverages the benefits of TGVs to simplify internal routing and potentially reduce the form factor of the OLED display.

The integration of a TGV-enabled glass substrate directly into an OLED display stack, to provide internal vertical interconnections to the display's transparent electrodes and TFT circuitry, is an obvious adaptation of known technologies in pursuit of established industry goals for display module design.

Independent Claim 15 Analysis

Claim 15: A method of manufacturing a glass substrate involving providing first and second nets of traces with gaps, inserting metal traces through these gaps, forming and curing a thermal resistance layer that permeates the second net and covers the metal traces, placing a mold, forming a fixed layer, introducing and solidifying a liquid glass layer in the mold, removing the mold, and cutting to produce first substrates with metal plugs.

Prior Art Combination: This manufacturing method is rendered obvious by combining the understanding of the challenges in forming TGVs (US9130016B2), with techniques for inserting pre-formed conductive elements into substrates and embedding them (as exemplified by the magnetic assembly of metal wires in via holes, discussed in "Development of Through Glass Vias (TGVs) for Interposer Applications" and "Through-Glass Vias for Glass Interposers and MEMS Packaging Applications Fabricated Using Magnetic Assembly of Microscale Metal Wires"), and general knowledge of molding, material solidification, and cutting processes in semiconductor manufacturing.

Rationale for Obviousness:

1. Need for Improved TGV Fabrication: Prior art explicitly states the difficulty and expense of forming micro through-holes in glass. This created a strong motivation for developing alternative, more cost-effective, and reliable TGV manufacturing methods.
2. Inserting Conductive Elements into Substrate Vias: The concept of inserting pre-formed metal elements (e.g., nickel wires) into pre-made via holes in a glass substrate and then encapsulating them was known. Specifically, the "magnetic assembly of metal wires" method described at KTH involved introducing nickel wires into via-holes in a glass substrate and applying a spin-on polymer to isolate them. This directly teaches the concept of using discrete "metal traces" and embedding them within a substrate using a polymer (thermal resistance layer).
3. Molding and Solidifying Glass: The use of molds to define the shape of a material and the process of forming a liquid glass layer which is then cooled to a solid state are fundamental manufacturing techniques. The patent itself refers to the "glass transition temperature" and the process of glass softening and melting. [Full patent text]
4. Structured Placement (Nets and Gaps): The "first and second nets" with "gaps" would be an obvious jig or fixture design to precisely position and hold the "metal traces" during the insertion and subsequent glass-forming steps, ensuring accurate TGV array formation. This would be a routine engineering solution to the challenge of aligning and securing multiple small components.
5. Post-Processing: The steps of removing the mold and cutting the resulting column to produce individual substrates are standard practices in manufacturing to obtain final products from a larger processed wafer or panel.

Given the known challenges in TGV fabrication and the existence of methods involving inserting metal wires into vias and embedding them, a POSA would be motivated to devise a manufacturing process using structured "nets" to guide metal traces, and then encasing them in glass via a molding and solidification process. This combination represents an obvious evolution of existing TGV manufacturing techniques to achieve greater precision, scalability, and cost-effectiveness.