Prior art

US patent 11894098, titled "Dynamic random access memory applied to an embedded display port," describes a dynamic random access memory (DRAM) configured for low power consumption, particularly for use as a frame buffer in an embedded display port (eDP) application. The invention primarily focuses on operating the various units of the DRAM (memory core, peripheral circuit, and input/output unit) at lower-than-standard voltages to reduce power consumption.

Specifically, the patent claims a DRAM that includes a memory core unit, a peripheral circuit unit, and in some embodiments, an input/output unit. A key feature is that the peripheral circuit unit operates at a second predetermined voltage lower than 1.1V, and in embodiments with an I/O unit, the I/O unit operates at a third predetermined voltage lower than 1.1V. The memory core unit can operate at a first predetermined voltage which may also be lower than 1.1V (e.g., Claim 4, Claim 7), or at approximately 1.8V (e.g., as discussed in reference to Table III in the Detailed Description). The architecture aims to significantly reduce system power consumption and extend battery life for portable devices.

Below is an analysis of the most relevant prior art cited in US11894098, focusing on patent citations and their potential to anticipate the claims under 35 U.S.C. § 102. It is important to note that a definitive legal determination of anticipation would require a full review of each cited patent's specification and claims, which is beyond the scope of this analysis. The potential anticipation is inferred from the titles and described subject matter.

Most Relevant Prior Art for US11894098

1. US20090122620A1 - Systems and Methods for Low Power, High Yield Memory

   • Full Citation: US20090122620A1 (Qualcomm Incorporated)
   • Publication/Filing Date: Publication Date: 2009-05-14; Priority Date: 2007-11-08
   • Brief Description: This patent application describes systems and methods for low power, high yield memory.
   • Potential Anticipation (35 U.S.C. § 102): The title directly mentions "Low Power...Memory," which is a core objective of US11894098. If this reference discloses a DRAM structure with various units (core, peripheral, I/O) operating at different, reduced voltages, especially where peripheral or I/O circuits are below 1.1V, it could potentially anticipate claims 1, 2, 3, 6, and 8. The general concept of reducing power in memory, and possibly specific voltage reduction techniques for different memory components, might be found here.

2. US20090067217A1 - Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same

   • Full Citation: US20090067217A1 ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.))
   • Publication/Filing Date: Publication Date: 2009-03-12; Priority Date: 2007-02-27
   • Brief Description: This patent application details methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using these methods.
   • Potential Anticipation (35 U.S.C. § 102): The title directly addresses "supplying power supply voltages in semiconductor memory devices." This suggests a focus on voltage management within memory. If this prior art teaches a DRAM with distinct power supply voltages for its core, peripheral, and I/O units, and particularly if those voltages are specifically defined to be below 1.1V for peripheral and/or I/O, it could potentially anticipate claims 1, 2, 3, 6, and 8. The concept of applying different, optimized voltages to different memory components for power saving is highly relevant.

3. US20100290300A1 - Semiconductor integrated device

   • Full Citation: US20100290300A1 (Nec Electronics Corporation)
   • Publication/Filing Date: Publication Date: 2010-11-18; Priority Date: 2009-05-14
   • Brief Description: This patent application describes a semiconductor integrated device.
   • Potential Anticipation (35 U.S.C. § 102): While the title is general ("Semiconductor integrated device"), if the detailed description of this patent (which is not available here) focuses on memory devices, particularly DRAM, and includes specific voltage reduction techniques for different internal units (core, peripheral, I/O) to achieve lower power consumption, it could potentially anticipate claims 1, 2, 3, 6, and 8. Given that power consumption is a common challenge in integrated circuits, it's plausible this patent addresses it in a memory context.

4. US20050133852A1 - High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines

   • Full Citation: US20050133852A1 (Jeng-Jye Shau)
   • Publication/Filing Date: Publication Date: 2005-06-23; Priority Date: 1996-05-24
   • Brief Description: This patent application describes high performance embedded semiconductor memory devices with multiple dimension first-level bit-lines.
   • Potential Anticipation (35 U.S.C. § 102): The title includes "embedded semiconductor memory devices," which is relevant to the "embedded display port" application of US11894098. While the primary focus appears to be on bit-line architecture and performance, any disclosure regarding power management strategies, particularly differential voltage application across memory components (e.g., core vs. periphery/I/O) within such embedded memory, could potentially anticipate elements of claims 1, 3, and 6 related to the component structure and general power-saving for embedded applications.

This analysis relies heavily on the titles of the cited patents. A thorough assessment of anticipation would require a detailed examination of each patent's full text, including its claims, figures, and detailed description, to determine if all elements of US11894098's claims are present in a single prior art reference, either explicitly or inherently.