Obviousness

The US patent 11894098, titled "Dynamic random access memory applied to an embedded display port," claims a dynamic random access memory (DRAM) characterized by its operating voltages for different internal units. The core innovation revolves around operating the memory core cell, peripheral circuit, and/or input/output (I/O) unit at lower-than-standard voltages, specifically with the peripheral and I/O units operating below 1.1V, and often with different voltages for these units. This design aims to significantly reduce power consumption, particularly when the DRAM acts as a frame buffer for an embedded display port (eDP) supporting panel self refresh (PSR).

An analysis under 35 U.S.C. § 103 for obviousness considers whether the claimed invention, as a whole, would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). This involves identifying relevant prior art, the differences between the prior art and the claimed invention, the level of ordinary skill in the art, and the motivation to combine the prior art references.

Claims of US11894098 (Key Features for Obviousness Analysis):

• Claim 1: A DRAM with a volatile DRAM core cell supplied with a first voltage (< 1.1V) and a peripheral circuit supplied with a second voltage (< 1.1V), where the first voltage is different from the second voltage. Both are on a single chip, with the peripheral external to the core.
• Claim 2: Similar to claim 1, but specifies the first voltage > the second voltage.
• Claim 3: A DRAM with a volatile DRAM core cell (supplied with a first voltage), an input/output circuit (supplied with a third voltage < 1.1V), and a peripheral circuit (supplied with a second voltage < 1.1V). The first voltage is different from the second and third voltages. Core and I/O are on a single chip, with I/O external to the core.
• Claim 4: (Dependent on claim 3) The first voltage is lower than 1.1V.
• Claim 6: A DRAM with a volatile DRAM core cell (supplied with a first voltage) and an input/output circuit (supplied with a third voltage < 1.1V), where the first voltage > the third voltage. The DRAM is capable of being applied to an embedded display port (eDP).
• Claim 8: (Dependent on claim 6) Further comprises a peripheral circuit supplied with a second voltage (< 1.1V).

The common thread is the use of distinct and low operating voltages (< 1.1V) for different functional units within a DRAM, especially for power reduction in eDP applications.

Identified Prior Art References:

Based on the "Citations" section of US11894098, the following references are highly relevant for an obviousness analysis:

1. US20090067217A1 ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)): "Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same"
2. US20090122620A1 (Qualcomm Incorporated): "Systems and Methods for Low Power, High Yield Memory"
3. Iyer, S.S.; Kalter, H.L., "Embedded DRAM technology: opportunities and challenges", Spectrum, IEEE (vol. 36, Issue: 4), Apr. 1999, IEEE, pp. 56-64. (Non-patent literature)

Motivation to Combine:

The "Background of the Invention" section of US11894098 explicitly identifies the problem addressed by the patent: the embedded display port (eDP) version 1.3, with its panel self refresh (PSR) function, can reduce graphic processing unit (GPU) power, but it increases power consumption of the timing controller due to the operation of the DRAM frame buffer. The patent states, "Therefore, how to design the frame buffer to reduce the power consumption of the timing controller becomes an important issue of memory manufacturers." This unequivocally establishes a strong motivation for a person having ordinary skill in the art (PHOSITA) to seek ways to reduce the power consumption of a DRAM acting as a frame buffer for an eDP.

A PHOSITA in the field of DRAM design for display applications, confronted with the stated problem of increased power consumption in eDP timing controllers, would be motivated to develop lower-power DRAM solutions.

Obviousness Argument:

The claims of US11894098 would be obvious under 35 U.S.C. § 103 by combining the teachings of US20090067217A1 (Samsung), US20090122620A1 (Qualcomm), and the well-understood problem in the art regarding eDP power consumption.

1. Multi-Voltage Architecture (Samsung): US20090067217A1 (Samsung) teaches methods for supplying power supply voltages in semiconductor memory devices. Notably, it describes a semiconductor memory device that includes a cell array (equivalent to a DRAM core cell) configured to operate with a first core voltage and a periphery circuit configured to operate with a second core voltage, where the first and second core voltages are different from each other. This directly teaches the fundamental concept of supplying different voltages to the core and peripheral units of a DRAM, addressing a key aspect of claims 1, 2, 3, 5, and 9.

2. Low-Power Memory Design (Qualcomm): US20090122620A1 (Qualcomm) focuses on "Systems and Methods for Low Power, High Yield Memory." This reference would inform a PHOSITA about various techniques for achieving low power in memory devices, which commonly include voltage scaling (i.e., reducing operating voltages) to minimize dynamic and static power dissipation.

3. Motivation to Apply to eDP (Background of US11894098 & General Knowledge): As highlighted in the background of US11894098, the eDP 1.3 standard with PSR created a specific need for low-power frame buffers to prevent the timing controller's power consumption from offsetting the GPU's power savings. The non-patent literature by Iyer and Kalter, "Embedded DRAM technology: opportunities and challenges," from 1999, further underscores the general importance of power considerations in embedded DRAM. A PHOSITA, aware of this problem and the general desirability of low-power solutions for portable devices, would be strongly motivated to apply known low-power techniques to DRAMs used as eDP frame buffers.

Reasoning for Obviousness of Specific Claim Features:

• Operating Voltages Lower Than 1.1V (Claims 1, 3, 4, 6, 7, 8): The patent itself notes that "the operation voltages specified by the Joint Electron Device Engineering Council (as shown in Table I) can not satisfy requirements... of the embedded display port (eDP) version 1.3." Table I shows JEDEC LPDDR II peripheral and I/O voltages in the range of 1.14V-1.30V. Given Qualcomm's teachings on low-power memory, and the explicit problem of insufficient power reduction with standard JEDEC voltages, it would be an obvious engineering design choice for a PHOSITA to further reduce the operating voltages of power-consuming units like the peripheral and I/O circuits below the then-current LPDDRII low-power specifications (i.e., below 1.1V) to achieve the desired "significantly reduced" power consumption. This specific numerical threshold represents an optimization to a known goal using known techniques.

• Different Voltages for Different Units (Claims 1, 2, 3, 5, 9): Samsung's patent explicitly teaches applying different operating voltages to the core and peripheral circuits of a semiconductor memory. Extending this concept to include an I/O unit (claim 3) would also be obvious, as I/O circuits are distinct functional blocks with their own voltage requirements and power consumption characteristics. The specific relationships, such as the core voltage being greater than the peripheral or I/O voltage (claims 2, 6), are common design considerations to ensure data retention stability in the core while maximizing power savings in other circuits that might be less sensitive to extreme voltage reduction.

• Application to Embedded Display Port (eDP) (Claim 6): Once a PHOSITA had conceived of a low-power, multi-voltage DRAM (by combining Samsung and Qualcomm), its application as a frame buffer for an eDP to address the explicitly stated problem of increased timing controller power consumption (as described in US11894098's background) would be a direct and obvious application.

In conclusion, the claimed invention in US11894098 would have been obvious to a person having ordinary skill in the art. The motivation to reduce power consumption in eDP timing controllers was clearly established. The prior art taught using different voltages for different functional units within a memory (Samsung) and provided general methods for achieving low-power memory through voltage scaling (Qualcomm). Combining these known techniques and applying them to the specific problem of eDP frame buffer power consumption, including making the obvious engineering choice to reduce voltages below existing low-power standards (e.g., below 1.1V for peripheral and I/O units), would have been well within the capabilities of a PHOSITA.