Prior art

To identify the most relevant prior art for US patent 11575381, I will first search the USPTO database for the patent and then examine its cited references.

US Patent 11575381 Information

• Patent Number: US11575381B1
• Title: Field programmable gate array with external phase-locked loop
• Publication Date: 2023-02-07
• Filing Date: 2022-04-18
• Assignee: HFT Solutions LLC
• Inventor: Nima Badizadegan
• Abstract: The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

The patent addresses the technical problem in FPGAs where phase synchronization between receiver-side and transmitter-side clock signals introduces unwanted latency, which is particularly undesirable in applications like high-frequency trading. The solution involves an external phase controller providing phase matching between a receiver clock and a transmitter clock used in the FPGA, without introducing unnecessary delay by eliminating the need for internal clock domain crossing circuits.

Most Relevant Prior Art for US11575381B1

To determine the most relevant prior art, I will examine the citations listed in the patent document. Since direct access to the full citation list and analysis of each reference is not possible in this format, I will focus on the explicitly mentioned prior art problem within the patent's background and summary.

The patent explicitly identifies a problem with the prior art related to clock synchronization in FPGAs:

• "One technological problem with FPGAs is that there is a need to synchronize receiving side and transmitting side clock signals within the FPGA. The prior art sought to address this problem by including a clock domain crossing circuit in the FPGA, however, these circuits inherently add a delay to the processing that takes place in the FPGA, which is not desirable since high frequency trading may include timestamps that are accurate to the microsecond such that even small delays may present a large problem."

This description indicates that any prior art disclosing the use of clock domain crossing (CDC) circuits within an FPGA for synchronizing receiver and transmitter clocks, which inherently introduce delay, would be highly relevant. The patent aims to overcome this specific limitation.

Without the specific list of "Prior Art References" that were cited by the examiner and applicant, I cannot provide a detailed breakdown of each patent citation. However, based on the patent's own discussion, the type of prior art that is most relevant is clear.

If I were to perform a manual search for prior art, I would look for patents and publications that describe:

1. FPGA systems with high-speed transceivers.
2. Methods and circuits for clock synchronization between different clock domains within an FPGA.
3. The use of Clock Domain Crossing (CDC) circuits (e.g., asynchronous FIFOs, asynchronous gearboxes, mesochronous clock crossing circuits) in FPGAs.
4. Discussion of latency concerns in FPGA-based high-frequency trading or similar low-latency applications due to clock synchronization methods.

The claims of US11575381B1 are directed towards a system and method that avoids the delays associated with internal clock domain crossing circuits by employing an external phase control circuit. Therefore, prior art that teaches internal CDC circuits for clock synchronization in FPGAs would be most relevant for potential anticipation under 35 U.S.C. § 102.

Key Claims potentially anticipated by the described prior art:

The core of the invention lies in avoiding internal CDC circuits for phase alignment by using an external phase control loop. Therefore, any claim that requires an external phase control or excludes an internal CDC for phase alignment would differentiate from the described prior art. Conversely, claims that broadly describe FPGA functionality, deserialization, serialization, or general clock generation/transmission, without the specific external phase control mechanism, might be more susceptible to anticipation by prior art that uses internal CDC for clock synchronization.

For example, independent claim 1 describes a field programmable gate array system including an FPGA and an external phase control circuit where the transmitter and receiver clock signals are phase aligned by the external control, specifically stating the "transmitter side clock signal and the receiver side clock signal are phase aligned so that there is a fixed phase difference between the third phase and the fifth phase." If a prior art document showed a system with all the elements of claim 1, but used an internal clock domain crossing circuit to achieve phase alignment, it would be highly relevant to argue anticipation or obviousness.

Without the ability to perform a live, in-depth search of cited references and their full contents, a specific list of anticipating claims for each prior art reference cannot be confidently generated. However, the conceptual framework provided above outlines how to evaluate such prior art.