Obviousness

The US patent 11575381, titled "Field programmable gate array with external phase-locked loop," addresses a technical problem in Field Programmable Gate Arrays (FPGAs) related to phase matching receiver-side and transmitter-side clock signals without introducing undesirable processing delays. The patent describes a system where an external phase control circuit, comprising a phase detector, a phase controller, and an adjustable oscillator, manages the phase alignment of clocks in an FPGA, thereby avoiding the latency associated with internal Clock Domain Crossing (CDC) circuits.

Based on the information provided within the patent document, the following prior art concepts and components can be identified:

Identified Prior Art References:

1. Conventional Field Programmable Gate Array (FPGA) System with Internal Clock Domain Crossing (CDC) (described in the Background and illustrated in FIG. 1): This prior art describes an FPGA (e.g., FPGA 100) that includes transceiver banks (102), a deserializer (104), a serializer (110), an FPGA Core (106) for computations, and an internal transceiver Phase-Locked Loop (PLL) (108). Crucially, this conventional system incorporates a "clock domain crossing circuit 112" within the FPGA to provide "phase matching or synchronizing" between the receiver and transmitter clocks. The system receives a "REFERENCE CLOCK signal" from an external "Oscillator or Clock Generator 122". The patent explicitly highlights a "significant drawback" of this internal CDC, stating that it "adds latency related to the phase difference between the clocks plus the latency of the synchronizers used, and does not perform any computation, such that it slows the effective processing speed of FPGA 100." This latency is particularly problematic for applications requiring sub-microsecond accuracy, such as high-frequency trading. [cite: FIG. 1, Background section, definitions for 'FPGA 100', 'FPGA Transceiver banks 102', 'deserializer 104', 'serializer 110', 'FPGA Core 106', 'transceiver PLL 108', 'Oscillator or Clock Generator 122', 'clock domain crossing circuit 112', 'One technological problem with FPGAs', 'the prior art', 'a significant drawback of the clock domain crossing circuit 112']
2. General Knowledge of External Phase-Locked Loop (PLL) Components and Concepts: The patent's detailed "Description" and "Definitions" sections enumerate various types of individual components known in the art for clock and phase control, which are standard elements of PLLs. These include:
   • Adjustable Oscillators: Described as "voltage controlled oscillators," "numerically/digitally-controlled oscillators," "digital delay line," and "voltage-controlled delay element." [cite: definitions for 'the adjustable oscillator 2200']
   • Phase Detectors: Described as various circuits such as "XOR gate," "S-R flip-flop," "D flip-flop," "Edge-triggered JK flip-flop," "Gilbert cell multiplier," "Diode ring mixer," and multi-bit "time-to-digital converter (TDC)" variants like "Vernier TDC," "parallel delay line TDC," "counter-based TDC," "interpolator TDC," "tapped delay line TDC," "metastability-based phase detector," "pulse-shrinking TDC," and "scrambling TDC." [cite: definitions for 'the phase detector 2206']
   • Phase Controllers (e.g., Loop Filters): The patent refers to a "controller 2202" that "utilizes a phase-locked loop" and "loop filter" components, describing their orders (first, second, third, fourth) and characteristics (e.g., derivative components). [cite: definitions for 'the controller 2202', 'the loop filter']

Obviousness Analysis under 35 U.S.C. § 103:

A person having ordinary skill in the art (PHOSITA) in FPGA design and high-speed digital systems, particularly those focused on low-latency applications, would have been motivated to combine elements from the identified prior art to arrive at the claimed invention, rendering it obvious.

Combination of Prior Art References:

The claimed invention is rendered obvious by combining Prior Art Reference 1 (Conventional FPGA with internal CDC and its recognized latency problem) with Prior Art Reference 2 (General knowledge of external PLL components and concepts for precise clock synchronization).

Motivation for Combination:

1. Clear Problem Statement and Motivation to Solve: Prior Art Reference 1, as described in the patent's "Background," unequivocally articulates a significant technical problem: the "unwanted latency" introduced by "clock domain crossing circuit 112" for phase synchronization within conventional FPGAs. This latency is deemed "not desirable" and a "large problem" for critical applications like high-frequency trading. [cite: Background section, definitions for 'One technological problem with FPGAs', 'the prior art', 'a significant drawback of the clock domain crossing circuit 112'] This explicit recognition of a severe drawback provides a strong and direct motivation for a PHOSITA to seek alternative solutions for phase alignment that minimize latency.

2. Known Solution Elements for Clock Control: PHOSITAs are thoroughly familiar with phase-locked loops as a standard and effective technique for generating, synchronizing, and aligning clock signals with high precision. Prior Art Reference 2 confirms that the individual building blocks of a PLL—phase detectors, phase controllers (loop filters), and adjustable oscillators—are well-known and readily available components in the field of electronics. The conventional FPGA (Prior Art Reference 1) itself uses an external "Oscillator or Clock Generator 122" to provide a "REFERENCE CLOCK signal," indicating that integrating external clocking and control elements with FPGAs is a known practice. [cite: definitions for 'a REFERENCE CLOCK signal']

3. Predictable Application to Address the Identified Problem: Given the problem of internal CDC latency (Prior Art Reference 1), a PHOSITA would naturally consider how to leverage external, precise clock control mechanisms (Prior Art Reference 2) to bypass or eliminate this latency. The logical steps for a PHOSITA would be:

   • Extract Critical Clock Signals: Recognizing that the internal CDC is intended to synchronize the receiver-side clock (generated by the deserializer) and the transmitter-side clock (used by the serializer), the PHOSITA would consider routing these clock signals outside the FPGA through dedicated pins. This allows for external monitoring and control. The patent's system in FIG. 2, for example, shows a first clock output pin transmitting the receiver-side clock and a second clock output pin transmitting the transmitter-side clock to an external phase detector. [cite: Summary section, FIG. 2, definitions for 'the second plurality of pins', 'first clock output pin', 'second clock output pin']
   • Implement an External Phase Control Loop: With the critical clock signals available externally, the PHOSITA would then design an external feedback loop using known PLL components (phase detector, phase controller, adjustable oscillator from Prior Art Reference 2). This external loop would compare the phases of the receiver and transmitter clocks, determine any difference, and generate adjustment information.
   • Control the FPGA's Clock Input: The adjustment information from the external phase controller would then be used to modify the clock signal provided by the external adjustable oscillator, which, in turn, feeds back into the FPGA to control the serializer's clock. This forms a closed-loop system that actively aligns the receiver and transmitter clocks. The patent describes the adjustable oscillator (2200) generating the second clock signal based on adjustment information from the phase controller (2202), and transmitting it to the second reference clock pin of the FPGA's first interface. [cite: Summary section, FIG. 2, definitions for 'a phase control circuit', 'adjustable oscillator 2200', 'phase controller 2202']
   • Eliminate the Internal Latency Source: By successfully implementing an external phase alignment mechanism, the internal CDC circuit (112) becomes redundant for its primary function of phase synchronization and can be removed or bypassed, directly achieving the desired reduction in processing latency. The patent's claims emphasize that "the first set of operations does not include clock domain crossing operations that delays processing of the first set of parallel data streams." [cite: Summary section, definitions for 'the first set of operations does not include clock domain crossing operations']

Therefore, the combination of a conventional FPGA system, where the latency of internal CDC circuits is a recognized problem, with the widely known and readily implementable principles and components of external phase-locked loops for precise clock control, would be obvious to a PHOSITA seeking to overcome the explicitly stated deficiencies of the prior art. The resulting system, as claimed, is a predictable application of known engineering principles to achieve a desired and clearly articulated improvement (reduced latency).