Prior art

To identify the most relevant prior art for US patent 11544183, I need to perform a search within the USPTO database for the patent's cited references. Since direct access to the USPTO database for specific patent citations and their detailed descriptions isn't available through my current tools, I will outline the general process a patent analyst would follow.

A patent analyst would typically use the USPTO Patent Public Search tool or similar patent databases to access the full patent document for US11544183. Within the patent document, there's a section titled "References Cited" (or similar) that lists all prior art considered by the patent examiner and the applicant. This list includes both U.S. Patents and potentially foreign patents or non-patent literature.

For each reference listed in US11544183, the analyst would:

1. Obtain the full citation: This includes the patent number, inventor(s), issue/publication date, and assignee.
2. Determine publication/filing date: For a U.S. patent, this would be the issue date; for a U.S. patent application publication, it would be the publication date. The filing date is also important for determining 35 U.S.C. § 102 anticipation.
3. Read the abstract and relevant sections: A brief description of the reference's technology, focusing on aspects that relate to the claims of US11544183.
4. Analyze for potential anticipation under 35 U.S.C. § 102: This involves comparing the elements of each independent claim (Claim 1, Claim 11, and Claim 16) of US115444183 against the disclosure of the prior art reference. Anticipation under § 102 means that every element of a claim is found, either explicitly or inherently, in a single prior art reference.

Without direct access to the USPTO's complete "References Cited" list and the full text of each cited patent, I cannot provide a definitive list of the most relevant prior art and their anticipating claims.

However, based on the patent summary provided, the core innovations of US11544183 relate to:

• Cooperative memory management between a memory controller and a host.
• The memory controller storing subdivision-specific memory data and making it accessible to the host.
• The host using this data to directly issue commands with physical addresses.
• Limited, self-correcting remapping by the memory controller for bad blocks, with eventual host awareness and update of translation tables.

Therefore, prior art that would be highly relevant for potential anticipation would likely include patents disclosing:

• Memory systems with host-controlled physical addressing for nonvolatile memory.
• Memory controllers that provide detailed usage statistics or metadata to a host.
• Techniques for bad block management in nonvolatile memory, particularly those involving cooperation between a controller and a host, or remapping schemes.
• Flash translation layers (FTLs) that are significantly simplified or offloaded to the host.

To provide the specific prior art details and their potential anticipatory effect, I would need to perform the detailed analysis described above using the full patent document.