Prior art

To identify the most relevant prior art for US patent 11347657, I will examine the "Cited by" section of the patent on the USPTO website. This section lists the patents and publications that the examiner considered during prosecution, as well as those cited by the applicant. Since I cannot directly access the USPTO database with specific queries at this moment, I will rely on the provided patent text which lists prior art keywords and priority claims.

The patent document US11347657B1 itself cites several documents as having priority or being incorporated by reference. These often represent critical prior art that the patent builds upon or distinguishes itself from.

Here's an analysis of the prior art mentioned within the patent document US11347657B1:

Priority/Incorporation by Reference Documents:

1. U.S. Utility patent application Ser. No. 16/808,304

   • Full Citation: U.S. Utility patent application Ser. No. 16/808,304, filed on Mar. 3, 2020, on behalf of first-named inventor Robert Lercari for “Nonvolatile memory controller supporting variable configurability and forward compatibility.”
   • Publication/Filing Date: March 3, 2020
   • Brief Description: This is a continuation of the application that led to US11347657, focusing on nonvolatile memory controllers supporting variable configurability and forward compatibility. As a direct lineage, it establishes the groundwork for the inventive concepts in US11347657, particularly around memory controller capabilities and addressing schemes.
   • Potential Anticipation (35 U.S.C. § 102): Since US11347657 is a continuation of this application, this document itself would not anticipate US11347657, as it shares the same inventive entity and effectively the same subject matter for priority purposes. It would serve as foundational disclosure rather than anticipatory prior art.

2. U.S. Utility patent application Ser. No. 15/690,006 (U.S. patent Ser. No. 10/642,748)

   • Full Citation: U.S. Utility patent application Ser. No. 15/690,006, filed on Aug. 29, 2017, on behalf of first-named inventor Robert Lercari for “Memory Controller with multimodal control over memory dies” (issued on May 5, 2020, as U.S. patent Ser. No. 10/642,748).
   • Publication/Filing Date: August 29, 2017 (filed); May 5, 2020 (issued)
   • Brief Description: This patent describes a memory controller with multimodal control over memory dies, which is a core concept in US11347657 regarding different operating modes (physical access, linearly virtualized, cooperative management, hierarchically virtualized).
   • Potential Anticipation (35 U.S.C. § 102): Similar to the above, this patent is part of the priority chain. The disclosed concepts of multi-modal control, exposing physical or pseudo-physical geometry, and hierarchical virtualization are fundamental to US11347657. Any claims in US11347657 that merely reiterate what is fully disclosed in this earlier patent without a novel distinction could potentially be anticipated. For example, the high-level description of a memory controller having multiple operating modes, including a hierarchically virtualized mode, could be anticipated if not further refined or combined with other elements in US11347657's claims.

3. U.S. Utility patent application Ser. No. 15/074,778 (U.S. Pat. No. 9,785,572)

   • Full Citation: U.S. Utility patent application Ser. No. 15/074,778, filed on Mar. 18, 2016, on behalf of first-named inventor Robert Lercari for “Expositive Flash Memory Control” (issued on Oct. 10, 2017, as U.S. Pat. No. 9,785,572).
   • Publication/Filing Date: March 18, 2016 (filed); October 10, 2017 (issued)
   • Brief Description: This patent introduces "Expositive Flash Memory Control," which is a foundational concept for the pseudo-expositive and hierarchically virtualized modes in US11347657. It likely details the mechanisms for exposing flash geometry to the host and managing it.
   • Potential Anticipation (35 U.S.C. § 102): As an earlier patent in the family, it could anticipate claims in US11347657 that are directly and identically disclosed in U.S. Pat. No. 9,785,572, especially those related to the fundamental aspects of expositive flash memory control and hierarchical address virtualization without additional distinguishing features.

4. U.S. Utility patent application Ser. No. 14/880,529 (U.S. Pat. No. 9,542,118)

   • Full Citation: U.S. Utility patent application Ser. No. 14/880,529, filed on Oct. 12, 2015, on behalf of first-named inventor Robert Lercari for “Expositive Flash Memory Control” (issued on Jan. 10, 2017, as U.S. Pat. No. 9,542,118).
   • Publication/Filing Date: October 12, 2015 (filed); January 10, 2017 (issued)
   • Brief Description: This is also titled "Expositive Flash Memory Control" and is a predecessor to U.S. Pat. No. 9,785,572. It would lay further groundwork for the concepts of exposing flash geometry and hierarchical virtualization.
   • Potential Anticipation (35 U.S.C. § 102): Similar to the other family members, any claims in US11347657 that are identically disclosed in U.S. Pat. No. 9,542,118 without further novel elements or arrangements could be anticipated. This would include core concepts of dividing an incoming memory address into discrete address fields corresponding to hierarchical groups of structural elements and using at least one virtual address field.

5. U.S. Provisional Patent Application No. 62/199,969

   • Full Citation: U.S. Provisional Patent Application No. 62/199,969, filed on Jul. 31, 2015, on behalf of first-named inventor Robert Lercari for “Expositive Flash Memory Control.”
   • Publication/Filing Date: July 31, 2015
   • Brief Description: A provisional application for "Expositive Flash Memory Control," providing an early disclosure of the concepts.
   • Potential Anticipation (35 U.S.C. § 102): Provisional applications establish an early filing date for the subject matter they disclose. If any claims in US11347657 are fully and identically disclosed in this provisional application, they would be covered by its priority date and thus not anticipated by it. However, if another reference predates this provisional application and discloses the same subject matter, that other reference could be anticipatory.

6. U.S. Provisional Patent Application No. 62/194,172

   • Full Citation: U.S. Provisional Patent Application No. 62/194,172, filed on Jul. 17, 2015, on behalf of first-named inventor Robert Lercari for “Techniques for Memory Controller Configuration.”
   • Publication/Filing Date: July 17, 2015
   • Brief Description: This provisional application focuses on techniques for memory controller configuration, which is relevant to how block devices are defined and allocated in US11347657.
   • Potential Anticipation (35 U.S.C. § 102): Similar to the above provisional, it sets an early priority date. Claims in US11347657 related to configurable block device allocation and memory controller configuration, if fully disclosed here, would be protected by this priority date against later art.

7. U.S. Provisional Patent Application No. 62/063,357

   • Full Citation: U.S. Provisional Patent Application No. 62/063,357, filed on Oct. 13, 2014, on behalf of first-named inventor Robert Lercari for “Techniques for Memory Controller Configuration.”
   • Publication/Filing Date: October 13, 2014
   • Brief Description: Another provisional application relating to memory controller configuration techniques.
   • Potential Anticipation (35 U.S.C. § 102): Establishes an even earlier priority date for memory controller configuration aspects.

8. U.S. Utility patent application Ser. No. 14/848,273

   • Full Citation: U.S. Utility patent application Ser. No. 14/848,273, filed on Sep. 8, 2015, on behalf of first-named inventor Andrey V. Kuzmin for “Techniques for Data Migration Based On Per-Data Metrics and Memory Degradation.”
   • Publication/Filing Date: September 8, 2015
   • Brief Description: This patent focuses on data migration techniques based on per-data metrics and memory degradation, a specific maintenance operation that can be managed by the memory controller described in US11347657.
   • Potential Anticipation (35 U.S.C. § 102): Claims in US11347657 that cover the specific data migration techniques detailed in this application, if fully disclosed here and not further distinguished, could be anticipated.

9. U.S. Provisional Patent Application No. 62/048,162

   • Full Citation: U.S. Provisional Patent Application No. 62/048,162, filed on Sep. 9, 2014, on behalf of first-named inventor Andrey V. Kuzmin for “Techniques for Data Migration Based On Per-Data Metrics and Memory Degradation.”
   • Publication/Filing Date: September 9, 2014
   • Brief Description: A provisional application for data migration techniques.
   • Potential Anticipation (35 U.S.C. § 102): Establishes priority for the data migration aspects described above.

10. U.S. Patent Publication 2014/0215129

    • Full Citation: U.S. Patent Publication 2014/0215129, for “Cooperative Flash Memory Control.”
    • Publication/Filing Date: Not explicitly stated, but the publication number indicates 2014.
    • Brief Description: This publication relates to "Cooperative Flash Memory Control," which is one of the operating modes (mode 116) discussed in US11347657. It involves the host receiving physical geometry and defining address assignments, with the memory controller assisting with statistics and maintenance notifications.
    • Potential Anticipation (35 U.S.C. § 102): Claims in US11347657 directed specifically to the "cooperative management mode" as described in Publication 2014/0215129, without further novel features, could be anticipated.

11. U.S. Utility patent application Ser. No. 14/047,193

    • Full Citation: U.S. Utility patent application Ser. No. 14/047,193, filed on Oct. 7, 2013, on behalf of first-named inventor Andrey V. Kuzmin for “Multi-Array Operation Support And Related Devices, Systems And Software.”
    • Publication/Filing Date: October 7, 2013
    • Brief Description: This application covers multi-array operation support, which is relevant to flash memory devices with multiple channels and dies.
    • Potential Anticipation (35 U.S.C. § 102): Any claims in US11347657 that describe basic multi-array operation in a flash memory system, if fully disclosed in this earlier application, could be anticipated.

General Note on Anticipation (35 U.S.C. § 102):

For a claim to be anticipated under 35 U.S.C. § 102, a single prior art reference must disclose every element of the claimed invention, either expressly or inherently, and the elements must be arranged as required by the claim. The disclosure must be identical to the claimed invention. Since many of the above listed references are part of the same patent family or are incorporated by reference, they establish the priority date for the claimed subject matter. Therefore, they would generally not anticipate the claims of US11347657 if those claims are adequately supported by the earlier filing dates of these documents. However, if any claims in US11347657 introduce new subject matter not explicitly or inherently disclosed in these earlier applications/patents, then other prior art that predates US11347657's effective filing date (and the priority dates of any new subject matter) could potentially anticipate those new claims. The above analysis focuses on how these cited documents relate to the present patent, rather than identifying external prior art.

To perform a thorough prior art analysis under 35 U.S.C. § 102, a patent examiner would typically conduct a comprehensive search of various public information sources, including other patents, publications, products, and public knowledge. The USPTO provides tools for searching its patent database.