Obviousness

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 11347657

This analysis assesses the obviousness of US Patent 11347657's independent claims (Claims 1, 10, and 16) in light of prior art, specifically focusing on US Patent 9,542,118 (Lercari et al.), which is a direct parent patent in the same family and explicitly referenced within the disclosure of US11347657. The earliest priority date for US11347657 is 2014-09-09. US Patent 9,542,118 was issued on January 10, 2017, from an application filed on October 12, 2015, and claims benefit of a provisional application filed on September 9, 2014 (U.S. Provisional Patent Application No. 62/048,162), which shares the earliest priority date with US11347657. Therefore, the teachings of US 9,542,118, particularly those derivable from its earliest priority date, are highly relevant prior art.

A person having ordinary skill in the art (PHOSITA) in the field of non-volatile memory systems would have been motivated to combine the teachings of the identified prior art to arrive at the claimed invention, particularly given the explicit overlap in objectives related to improving flash memory performance, predictability, and management.

Combination of Prior Art: US Patent 9,542,118 (Lercari et al.)

US Patent 9,542,118, titled "Expositive Flash Memory Control," discloses a substantial portion of the subject matter claimed in US11347657. The abstract of US 9,542,118 provides a comprehensive overview that closely aligns with the independent claims of US11347657.

Obviousness of Independent Claim 1 (Method for Memory Controller):

Claim 1 describes a method for a memory controller to manage a non-volatile memory system, involving:

1. Receiving a logical memory address (LBA) and a block device identifier from a host.
2. Retrieving block device configuration information, including an address space layout (ASL).
3. Subdividing the LBA into hierarchical sub-addresses, with at least one being a virtual address.
4. Translating the virtual address into a physical address using a lookup table.
5. Performing a memory operation using the physical addresses.

US 9,542,118 explicitly teaches a "memory controller that subdivides an incoming memory address into multiple discrete address fields corresponding to respective hierarchical groups of structural elements... and in which at least one of the discrete address fields constitutes a virtual address for the corresponding physical element within the structural hierarchy." This directly covers the subdivision of LBAs into hierarchical sub-addresses with at least one virtual address.

Furthermore, US 9,542,118 also discloses that "the net storage volume of a nonvolatile semiconductor memory system is subdivided into discrete performance-isolated storage regions... each such storage region being mapped by an independent linear range of logical addresses." These regions "may be presented to one or more host access requestors as an independent block device... each having its own performance characteristics and address space." The patent further states that "the mapping of the logical address space within a given block device, referred to herein as 'address space layout,' may vary from one block device to another... to yield configurable and varied block device characteristics in terms of endurance and I/O bandwidth." This disclosure clearly describes the use of block devices, their associated configuration (including ASL), and the use of identifiers to manage them.

Regarding the translation of virtual addresses, US 9,542,118 states that this "hierarchical subdivision" allows the virtual address "to be freely mapped to any of the constituent physical elements of that larger structure." It also highlights that "this architecture provides for greatly simplified address translation (e.g., which can optionally be implemented entirely in hardware), and facilitates configurable and predictable I/O latency." While "lookup table" is not explicitly in the abstract of 9,542,118, implementing such hardware-based address translation for virtual-to-physical mapping would be a conventional and obvious choice for a PHOSITA in designing high-performance memory controllers once the concept of hierarchical virtualization is established.

Motivation to Combine/Modify: A PHOSITA, seeking to implement a memory controller with the benefits of hierarchical virtualization and configurable block devices as taught by US 9,542,118, would find it obvious to use common data structures like lookup tables in hardware to perform the necessary address translations efficiently, especially for "greatly simplified" and "predictable I/O latency" operations. The explicit mention of hardware implementation in US 9,542,118 provides direct motivation for this design choice.

Obviousness of Independent Claim 10 (Memory Controller Apparatus):

Claim 10 describes a memory controller apparatus with a host interface, a flash interface, and control logic configured to perform steps analogous to Claim 1.

The apparatus claim follows directly from the method claim. The abstract of US 9,542,118 comprehensively describes the functional capabilities of such a memory controller, including its interaction with a host (receiving LBAs) and its management of non-volatile memory (performing operations on physical elements). The concept of a memory controller having control logic to execute these functions is fundamental. US11347657 also discusses its implementation as a "memory controller integrated circuit (IC)" featuring "hardware translation circuitry" and "lookup tables" (FIG. 14 description). Since US 9,542,118 is a parent patent, these implementation details are highly likely to be disclosed or obvious from its full specification.

Motivation to Combine/Modify: A PHOSITA designing a memory controller based on the principles of US 9,542,118 would find it obvious to incorporate the necessary control logic and hardware components (like interfaces and translation circuitry, including lookup tables) to achieve the described hierarchical address virtualization and block device management. These are standard architectural elements for a memory controller designed to achieve the performance goals articulated in US 9,542,118.

Obviousness of Independent Claim 16 (Non-Transitory Computer-Readable Medium):

Claim 16 describes a non-transitory computer-readable medium storing instructions that, when executed, perform a method comprising:

1. Configuring a non-volatile memory system to present a pseudo-physical geometry to a host.
2. Receiving an LBA from the host aligning with the pseudo-physical geometry, the LBA including at least one virtual address field.
3. Mapping the LBA to a physical storage location by translating the virtual address field to a physical address, thereby transparently skipping a defective or reserved physical element and maintaining the pseudo-physical geometry.

US 9,542,118 explicitly describes presenting an "idealized or pseudo-physical description of the underlying geometry" to the host. It also states that the memory controller maintains this "static idealized perspective" by "holding in reserve some number of erase units (or dies or any other resource likely to fail over time)." This directly teaches the concept of configuring a pseudo-physical geometry with configurable quantities of structural elements.

Furthermore, US 9,542,118 teaches that the memory controller is "free, by virtue of one or more virtualized address fields within the incoming logical addresses, to virtualize localized groups of physical structures and thus mask defective structural elements and swap operational structural elements into and out of service, for example, as they wear or otherwise require maintenance." This directly covers receiving an LBA with a virtual address field and mapping it to a physical location while transparently skipping defective or reserved elements, thereby maintaining the pseudo-physical geometry.

Motivation to Combine/Modify: A PHOSITA developing firmware or software for a memory controller based on US 9,542,118 would find it obvious to program instructions to implement the disclosed methods of configuring pseudo-physical geometry, processing LBAs with virtual address fields, and transparently managing defective or reserved physical elements. The ability to mask defects and maintain a consistent, idealized view for the host is a core benefit articulated in US 9,542,118, providing strong motivation for a PHOSITA to implement these features.

In conclusion, the independent claims of US Patent 11347657 would have been obvious to a person having ordinary skill in the art based on the teachings of US Patent 9,542,118 alone, which, as a direct parent patent, provides comprehensive disclosure of the key elements and their underlying principles. The advancements in US11347657 appear to be logical extensions or specific implementations of the broad concepts already laid out in US 9,542,118.