Prior art

To identify the most relevant prior art for US patent 11347656, I will examine the citations listed within the patent itself. The patent document provides a "PRIORITY/INCORPORATION BY REFERENCE" section that lists several related applications and patents. These typically represent the most relevant prior art identified during the examination process.

Here's an analysis of the prior art explicitly cited in US Patent 11347656:

1. U.S. Utility patent application Ser. No. 16/808,304

• Full Citation: U.S. Utility patent application Ser. No. 16/808,304, filed on Mar. 3, 2020.
• Publication/Filing Date: March 3, 2020.
• Brief Description: Titled "Nonvolatile memory controller supporting variable configurability and forward compatibility." This application appears to be a direct predecessor, continuing the concepts of flexible memory controller operation and compatibility across generations, which are central to US11347656.
• Potential Anticipation (35 U.S.C. § 102): This application likely anticipates claims relating to hierarchical address virtualization, configurable block device allocation, predictable I/O latency, and forward compatibility, as these are directly mentioned in its title and the descriptions within US11347656. This could potentially anticipate aspects of Claims 1, 11, 12, and 18, particularly the methods and systems for varying configurability and supporting forward compatibility.

2. U.S. Utility patent application Ser. No. 15/690,006 (U.S. patent Ser. No. 10/642,748)

• Full Citation: U.S. Utility patent application Ser. No. 15/690,006, filed on Aug. 29, 2017 (issued on May 5, 2020 as U.S. patent Ser. No. 10/642,748).
• Publication/Filing Date: August 29, 2017 (filing); May 5, 2020 (issue).
• Brief Description: Titled "Memory Controller with multimodal control over memory dies." This patent introduces the concept of a multi-modal memory controller, which is foundational to the various operating modes (physical access, linearly virtualized, cooperative management, hierarchically virtualized) discussed in US11347656.
• Potential Anticipation (35 U.S.C. § 102): This reference could potentially anticipate claims relating to memory controllers with multiple operating modes and the general architecture for controlling memory dies in different ways. This may impact the broader scope of Claims 1, 11, 12, and 18, especially concerning the memory controller's ability to operate in different modes and manage memory hierarchy.

3. U.S. Utility patent application Ser. No. 15/074,778 (U.S. Pat. No. 9,785,572)

• Full Citation: U.S. Utility patent application Ser. No. 15/074,778, filed on Mar. 18, 2016 (issued on Oct. 10, 2017 as U.S. Pat. No. 9,785,572).
• Publication/Filing Date: March 18, 2016 (filing); October 10, 2017 (issue).
• Brief Description: Titled "Expositive Flash Memory Control." This patent likely introduces the core concepts of "expositive" or "pseudo-expositive" memory control, where the memory controller exposes an idealized view of the flash geometry to the host, managing underlying complexities like bad blocks transparently. This is a crucial element of US11347656's hierarchical virtualization.
• Potential Anticipation (35 U.S.C. § 102): This reference directly anticipates the pseudo-expositive memory control, which is fundamental to the hierarchical address virtualization and decoupled bad block management described in US11347656. Specifically, this could anticipate aspects of Claims 1, 11, 12, and 18 that relate to abstracting the physical memory geometry from the host and managing bad blocks through virtualization.

4. U.S. Utility patent application Ser. No. 14/880,529 (U.S. Pat. No. 9,542,118)

• Full Citation: U.S. Utility patent application Ser. No. 14/880,529, filed on Oct. 12, 2015 (issued on Jan. 10, 2017 as U.S. Pat. No. 9,542,118).
• Publication/Filing Date: October 12, 2015 (filing); January 10, 2017 (issue).
• Brief Description: Also titled "Expositive Flash Memory Control." This appears to be an earlier iteration or related application to the one above, further detailing the "expositive flash memory control" concept.
• Potential Anticipation (35 U.S.C. § 102): Similar to Ser. No. 15/074,778, this reference would also anticipate elements of hierarchical address virtualization and decoupled bad block management, affecting Claims 1, 11, 12, and 18.

5. U.S. Provisional Patent Application No. 62/199,969

• Full Citation: U.S. Provisional Patent Application No. 62/199,969, filed on Jul. 31, 2015.
• Publication/Filing Date: July 31, 2015.
• Brief Description: Titled "Expositive Flash Memory Control." This is a provisional application supporting the "Expositive Flash Memory Control" lineage.
• Potential Anticipation (35 U.S.C. § 102): This provisional application provides an even earlier priority date for the core "Expositive Flash Memory Control" concepts, potentially anticipating aspects of Claims 1, 11, 12, and 18.

6. U.S. Provisional Patent Application No. 62/194,172

• Full Citation: U.S. Provisional Patent Application No. 62/194,172, filed on Jul. 17, 2015.
• Publication/Filing Date: July 17, 2015.
• Brief Description: Titled "Techniques for Memory Controller Configuration." This provisional application likely focuses on the configurability aspects of the memory controller, which are crucial for defining block devices and their characteristics in US11347656.
• Potential Anticipation (35 U.S.C. § 102): This could anticipate aspects of Claims 1, 11, 12, and 18 related to configuring the memory controller and defining block devices based on specified system requirements.

7. U.S. Provisional Patent Application No. 62/063,357

• Full Citation: U.S. Provisional Patent Application No. 62/063,357, filed on Oct. 13, 2014.
• Publication/Filing Date: October 13, 2014.
• Brief Description: Titled "Techniques for Memory Controller Configuration." Another provisional application related to memory controller configuration.
• Potential Anticipation (35 U.S.C. § 102): Similar to the previous provisional, this would anticipate elements of memory controller configuration and block device allocation, potentially affecting Claims 1, 11, 12, and 18.

8. U.S. Utility patent application Ser. No. 14/848,273

• Full Citation: U.S. Utility patent application Ser. No. 14/848,273, filed on Sep. 8, 2015.
• Publication/Filing Date: September 8, 2015.
• Brief Description: Titled "Techniques for Data Migration Based On Per-Data Metrics and Memory Degradation." This application deals with data migration and memory degradation, which are relevant to the maintenance operations and wear-leveling mentioned in US11347656.
• Potential Anticipation (35 U.S.C. § 102): This could anticipate aspects of Claims 1, 11, 12, and 18 related to memory management, maintenance operations, and data migration, especially when the memory controller cooperates with a host for these tasks.

9. U.S. Provisional Patent Application No. 62/048,162

• Full Citation: U.S. Provisional Patent Application No. 62/048,162, filed on Sep. 9, 2014.
• Publication/Filing Date: September 9, 2014.
• Brief Description: Titled "Techniques for Data Migration Based On Per-Data Metrics and Memory Degradation." A provisional application for the above.
• Potential Anticipation (35 U.S.C. § 102): Provides an earlier priority date for the concepts of data migration and memory degradation, potentially anticipating aspects of Claims 1, 11, 12, and 18 related to these functions.

10. U.S. Patent Publication 2014/0215129

• Full Citation: U.S. Patent Publication 2014/0215129, for "Cooperative Flash Memory Control."
• Publication/Filing Date: Not explicitly stated as a filing date, but as a publication, its effective date is prior to or on 2014/0215129.
• Brief Description: Titled "Cooperative Flash Memory Control." This publication describes a cooperative management mode where the host is aware of flash geometry and is notified of maintenance needs by the memory controller. This is an explicit mode described in US11347656.
• Potential Anticipation (35 U.S.C. § 102): This publication directly anticipates the "cooperative management mode" described in US11347656, which involves the host's awareness of flash geometry and shared management responsibilities. This could potentially anticipate aspects of Claims 1, 11, 12, and 18 regarding different modes of memory control and the interaction between the host and memory controller for management tasks.

11. U.S. Utility patent application Ser. No. 14/047,193

• Full Citation: U.S. Utility patent application Ser. No. 14/047,193, filed on Oct. 7, 2013.
• Publication/Filing Date: October 7, 2013.
• Brief Description: Titled "Multi-Array Operation Support And Related Devices, Systems And Software." This application likely deals with managing multiple memory arrays, which is relevant to the hierarchical structure of flash memory devices described in US11347656.
• Potential Anticipation (35 U.S.C. § 102): This could anticipate aspects of Claims 1, 11, 12, and 18 related to the overall architecture and management of multi-array memory systems and the underlying physical hierarchy.

It's important to note that many of these citations are part of the same patent family or describe closely related work by the same inventors/assignee. While they are prior art, they often represent a progression of inventive concepts. The "potential anticipation" is based on the descriptions provided within US11347656 itself, which often introduces these prior works as foundational or predecessor technologies. A detailed claim-by-claim analysis against each prior art document would be required for a definitive determination of anticipation.