Obviousness

Obviousness Analysis of US Patent 11347656 under 35 U.S.C. § 103

This analysis evaluates the obviousness of US Patent 11347656 ("the '656 patent") based on combinations of prior art, focusing on the concepts of hierarchical address virtualization and configurable block device allocation. The critical date for prior art is September 9, 2014, the priority date of the '656 patent.

Primary Prior Art Reference

Based on the explicit incorporation by reference and description within the '656 patent, U.S. Patent Publication 2014/0215129 A1 ("Cooperative Flash Memory Control" or "the '129 publication"), published on July 31, 2014, serves as a primary prior art reference. The '656 patent describes its "hierarchically virtualized mode" (element 118 in FIG. 1) as taking the "cooperative management mode" (element 116 in FIG. 1) a "significant step forward." The '129 publication, titled "Cooperative Flash Memory Control," is understood to describe this "cooperative management mode."

For the purpose of this analysis, and in the absence of the full text of US 2014/0215129 A1, we assume the '129 publication discloses a storage system with a memory controller and nonvolatile memory operating in a "cooperative management mode" as described in US11347656B1. This mode would include:

• A storage system comprising a memory controller and nonvolatile memory.
• The memory controller exposing the underlying physical flash geometry to a host.
• The host requesting and receiving a physical geometry description from the memory controller (a "geometry export").
• The host defining an address assignment where its linear logical block address (LBA) range is mapped directly onto the physical block addresses (PBAs) within the underlying flash storage.
• Defective or unavailable physical units (e.g., erase units) being reported to the host by the memory controller, and the host noting these defects within its LBA-to-PBA address map.
• This approach offers performance benefits (e.g., minimal I/O latency due to direct LBA-to-PBA mapping by the host), but places a significant burden on the host for media management tasks such as wear leveling, garbage collection, data scrubbing, and avoidance of failed structural elements.

Analysis of Independent Claims against Primary Prior Art

We will analyze the independent claims of US11347656B1 in view of the assumed disclosure of US 2014/0215129 A1.

Independent Claim 1 (Storage System):

• "A storage system comprising a memory controller and nonvolatile memory." This element is clearly disclosed by the '129 publication in its description of a flash device and memory controller.
• "the memory controller configured to receive a logical address (LBA) from a host." Disclosed by the '129 publication, as the host issues LBAs (or PBAs in cooperative mode) for memory access.
• "subdivide the logical address (LBA) into a plurality of discrete address fields corresponding to respective hierarchical groups of structural elements within the nonvolatile memory, the hierarchical groups of structural elements including channels, dies, erase units, and pages." The '129 publication, in "cooperative management mode," describes the host being "fully aware of the underlying flash device geometry" which includes hierarchical elements like dies and erase units. While the host manages the LBA-to-PBA mapping, the explicit subdivision of the LBA by the memory controller into discrete hierarchical address fields, where some are virtual, is not directly taught by the "cooperative management mode" description. In that mode, the LBA is often treated as a direct PBA by the host, or the host performs its own mapping to physical addresses.
• "wherein at least one of the plurality of discrete address fields constitutes a virtual address for a corresponding physical element within the hierarchical groups of structural elements," This is a key distinguishing feature. In the '129 publication's "cooperative management mode," defective units are reported to the host, implying a direct physical awareness by the host, not a virtualization by the controller that masks defects transparently. The address fields are effectively physical from the host's perspective.
• "and translate the virtual address to a physical address." This translation by the memory controller, transparent to the host for specific hierarchical levels, is also not taught by the "cooperative management mode."
• "and resolve a memory access based on the physical address and any other physical address fields of the plurality of discrete address fields." While memory access is resolved based on physical addresses, the method of deriving these physical addresses through selective virtualization and translation by the controller is not disclosed.

Independent Claim 11 (Method of Operation):
Similarly, the method steps of Claim 11 related to the memory controller subdividing the LBA into discrete address fields with at least one being virtual, and the controller translating this virtual address to a physical address are not explicitly taught by the '129 publication's "cooperative management mode." The '129 publication places the burden of managing physical addresses and defects largely on the host.

Independent Claim 12 (Memory Controller):
The memory controller in Claim 12, specifically its "address generation logic configured to... subdivide the LBA into discrete address fields... identify at least one of the discrete address fields as a virtual address, and translate the virtual address to a physical address," reflects the same distinguishing features missing from the '129 publication.

Independent Claim 18 (Non-transitory machine-readable medium):
This claim is dependent on Claim 11 and would therefore also be rendered obvious if Claim 11 is obvious.

Motivation to Combine

A person having ordinary skill in the art (PHOSITA) in data storage systems, upon reviewing the "cooperative management mode" disclosed in the '129 publication, would readily identify a significant problem: the substantial burden placed on the host for managing complex and hardware-specific media management tasks (e.g., bad block management, wear-leveling, garbage collection). This burden complicates host design, increases development costs, and necessitates significant re-design with each new generation of flash memory.

The PHOSITA would be motivated to reduce the host's management burden while retaining the performance advantages (e.g., predictable I/O latency) offered by the host's physical awareness in the cooperative management mode, and avoiding the performance degradation and capacity loss associated with a fully opaque Flash Translation Layer (FTL).

The solution lies in finding a middle ground. Known in the art at the time of the invention was the concept of hierarchical memory addressing, where memory is organized into distinct levels (e.g., channels, dies, erase units, pages). Also known was the use of virtual addressing to abstract physical resources, particularly for managing defective blocks in memory systems.

A PHOSITA would therefore be motivated to combine:

1. The "cooperative management mode" of the '129 publication: This provides the foundation of exposing underlying geometry and allowing the host to largely dictate address assignments for performance.
2. General knowledge of hierarchical memory addressing: The idea of subdividing an LBA into distinct fields corresponding to channels, dies, erase units, and pages is a fundamental aspect of addressing in flash memory systems.
3. General knowledge of virtual addressing and defect management: It is well-known that virtual addressing can be used to mask physical defects or re-locate data without informing the higher-level caller.

Specific Motivation to Combine to Achieve the '656 Patent's Invention:

The motivation to introduce selective hierarchical virtualization by the memory controller (as in the '656 patent) would be to:

• Mask defects transparently from the host: Instead of reporting every bad block (e.g., erase unit) to the host and requiring the host to update its maps (as in '129), the memory controller can virtualize only the erase unit level (or other localized levels). This allows the controller to remap defective erase units to spare ones within the same die without the host ever knowing, thus maintaining the host's idealized view of a "defect-free" block. This directly addresses the host's burden of managing failed structural elements.
• Simplify host management: By offloading localized defect management and wear leveling (through transparent remapping of virtualized segments) to the controller, the host's software becomes simpler and more portable across different flash generations. This directly addresses the complexity and re-design issues.
• Maintain performance predictability: By virtualizing only select hierarchical levels (e.g., erase units) and maintaining physical boundaries at higher levels (e.g., channels, dies) as reported to the host, the host can still schedule I/O operations with awareness of higher-level parallel resources, thus avoiding resource conflicts and preserving predictable I/O latency. This is a direct improvement over a full FTL which obscures all physical reality.
• Enable configurable block devices: The ability to present different "block devices" with varied performance characteristics by altering the address space layout (ASL) within the controller, and doing so while masking underlying physical complexities, would be a natural extension to cater to diverse application requirements. This allows a user/designer to specify high-level performance needs without delving into individual physical resource allocation.

Therefore, a PHOSITA, seeking to alleviate the host's burden of managing physical defects and complex media management tasks in the cooperative management mode (as taught by '129 publication), while preserving performance predictability, would find it obvious to apply known hierarchical addressing techniques in conjunction with selective virtual addressing within the memory controller. By doing so, the controller could subdivide an LBA into hierarchical fields, treat specific fields (e.g., erase unit addresses) as virtual for internal remapping, and translate these virtual addresses to physical addresses, thereby presenting a simplified, pseudo-physical, and defect-free view to the host. This combination of existing techniques to solve a known problem would be obvious to a PHOSITA.