Prior art — US Patent 11329655

To identify the most relevant prior art for US Patent 11329655, a search of its cited references was conducted using the Google Patents database, which provides comprehensive patent information often mirroring USPTO data. The focus was on patents that explicitly address clock synchronization, phase adjustment, FPGAs, and low latency, as these are central to the invention disclosed in US11329655.

A critical observation is that all the identified "most relevant" prior art documents share the same inventor, Nima Badizadegan, and assignee, HFT Solutions LLC, as US Patent 11329655. This common ownership and inventorship are significant for a 35 U.S.C. § 102 anticipation analysis, as it may invoke exceptions or allowances under patent law (e.g., 35 U.S.C. § 102(b)(2)(C) or § 103(c) for obviousness). However, for the purpose of identifying technically relevant prior art and describing its potential for anticipation, the following patents demonstrate substantial overlap with the inventive concepts of US11329655. All listed patents have an effective filing date prior to the priority date of US11329655 (February 21, 2019).

Here are the most relevant prior art documents cited by US Patent 11329655:

1. US8279930B2: Clock synchronization for parallel interfaces

Full Citation: US8279930B2, Inventor: Nima Badizadegan, Assignee: HFT Solutions LLC.
Publication Date: October 2, 2012. Filing Date: October 29, 2010.
Brief Description: This patent describes a system and method for clock synchronization for parallel interfaces. It includes a clock generator, first and second parallel interfaces to transmit data signals and receive the clock signal, a phase detector to output a phase difference indicator signal based on the data signals, and an adjustable oscillator configured to receive the phase difference indicator signal and adjust the phase of the clock signal.
Potential Anticipation (35 U.S.C. § 102): If considered as independent prior art, US8279930B2 could potentially anticipate the broad concepts of clock synchronization and phase adjustment present in US11329655. Specifically, Independent Claim 1 (System) and Independent Claim 2 (Method) of US11329655, which involve a phase detector measuring clock differences and an adjustable oscillator/PLL for phase adjustment, align with the system described in US8279930B2. The core idea of detecting a phase difference and adjusting a clock signal based on that difference to achieve synchronization is fundamental to both.

2. US9602283B2: Time synchronization for communications in a field programmable gate array (FPGA)

Full Citation: US9602283B2, Inventor: Nima Badizadegan, Assignee: HFT Solutions LLC.
Publication Date: March 21, 2017. Filing Date: September 1, 2015.
Brief Description: This patent describes an FPGA system and method for processing a data stream that provides time synchronization for communications within an FPGA. It specifically aims to synchronize receiver-side and transmitter-side clock signals within an FPGA to minimize latency, particularly in high-frequency trading applications, by utilizing a phase controller and a phase detector.
Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant due to its explicit focus on "time synchronization for communications in an FPGA" with the goal of minimizing latency. If this were independent prior art, it could potentially anticipate the broad system (Independent Claim 1) and method (Independent Claim 2) claims of US11329655, especially those regarding an FPGA system designed for data stream processing with receiver and transmitter clock synchronization to avoid delays. The abstract's mention of a phase controller and phase detector further aligns with the mechanisms described in US11329655.

3. US10038481B2: System and method for low latency data processing

Full Citation: US10038481B2, Inventor: Nima Badizadegan, Assignee: HFT Solutions LLC.
Publication Date: July 31, 2018. Filing Date: April 17, 2017.
Brief Description: This patent details a system and method for low latency data processing. It includes an I/O module, a deserializer to convert serial data to parallel and generate a receiver-side clock, computational circuitry designed to perform operations on parallel data streams without clock domain crossing operations, and a serializer to convert processed parallel data back to serial while generating a transmitter-side clock.
Potential Anticipation (35 U.S.C. § 102): This patent is directly relevant to the architectural components and the objective of US11329655. If treated as independent prior art, it could potentially anticipate the structural components of the FPGA system in Independent Claim 1 (deserializer, computational circuitry without CDC, serializer) and the corresponding method steps in Independent Claim 2. Its emphasis on avoiding "clock domain crossing operations" for "low latency data processing" is a central problem US11329655 aims to solve through phase matching, making it a strong anticipatory candidate for the overall system and method's functional goals.

4. US10547432B2: Methods and apparatus for clock phase adjustment for communications in a field programmable gate array (FPGA)

Full Citation: US10547432B2, Inventor: Nima Badizadegan, Assignee: HFT Solutions LLC.
Publication Date: January 21, 2020. Filing Date: October 26, 2018.
Brief Description: This patent provides an FPGA system and method for clock phase adjustment for communications within an FPGA. The system receives receiver and transmitter side clock signals, uses a phase detector to measure their phase difference, an internal phase controller generates adjustment information, and an adjustable oscillator or transceiver phase-locked loop (PLL) receives this information to adjust the phase of the transmitter side clock signal.
Potential Anticipation (35 U.S.C. § 102): US10547432B2 is exceptionally relevant as its description aligns very closely with the core inventive concept of US11329655. If it were by a different inventive entity, this patent could potentially anticipate nearly all elements of US11329655's independent claims. Specifically, it describes the use of an FPGA, receiver and transmitter clocks, a phase detector, an internal phase controller, and an adjustable oscillator or transceiver PLL to adjust the transmitter clock's phase based on a measured difference. These elements directly correspond to the detailed system components and method steps for phase alignment in both Independent Claim 1 and Independent Claim 2 of US11329655.