Obviousness

To analyze the obviousness of US patent 11329655 under 35 U.S.C. § 103, we will consider combinations of the provided prior art references and the motivation a person having ordinary skill in the art (PHOSITA) would have to combine them. The core of US11329655 lies in an FPGA system and method that provides internal phase matching between receiver-side and transmitter-side clocks to minimize latency by avoiding traditional clock domain crossing (CDC) operations, especially in high-frequency trading applications. This is achieved through a feedback loop involving an internal phase controller, a phase detector, and an adjustable phase-locked loop (PLL) or oscillator. All identified prior art references share the same inventor and assignee as US11329655 and have effective filing dates prior to its priority date of February 21, 2019, suggesting a continuous development effort in this specific technical area.

Combination 1: US9602283B2 in view of US10038481B2 and US10547432B2

A PHOSITA in the field of FPGA design for high-performance, low-latency data processing (e.g., for high-frequency trading) would find the invention claimed in US11329655 obvious by combining the teachings of US9602283B2, US10038481B2, and US10547432B2.

• US9602283B2 (Time synchronization for communications in a field programmable gate array (FPGA)) directly articulates the problem and high-level solution that US11329655 addresses. It describes an "FPGA system and method for processing a data stream that provides time synchronization for communications within an FPGA," specifically aiming to "synchronize receiver-side and transmitter-side clock signals within an FPGA to minimize latency, particularly in high-frequency trading applications, by utilizing a phase controller and a phase detector". This reference establishes the fundamental motivation for a PHOSITA to integrate precise clock synchronization into an FPGA architecture to meet the demands of low-latency applications like high-frequency trading.

• US10038481B2 (System and method for low latency data processing) provides the architectural framework necessary for a low-latency FPGA data processing system. It discloses an FPGA system with a deserializer to convert serial data to parallel and generate a receiver-side clock, computational circuitry designed to perform operations on parallel data streams without clock domain crossing operations to achieve low latency, and a serializer to convert processed parallel data back to serial while generating a transmitter-side clock. This patent details the crucial structural components of the FPGA system and emphasizes the avoidance of CDC operations as a means to minimize processing delays, which is a key feature of US11329655.

• US10547432B2 (Methods and apparatus for clock phase adjustment for communications in a field programmable gate array (FPGA)) teaches the specific mechanism for internal clock phase adjustment within an FPGA that is central to US11329655. It describes an FPGA system that receives receiver and transmitter side clock signals, employs a phase detector to measure their phase difference, utilizes an internal phase controller to generate adjustment information, and directs this information to an adjustable oscillator or transceiver phase-locked loop (PLL) to adjust the phase of the transmitter-side clock signal. These elements directly provide the means for implementing the phase matching identified as essential in US9602283B2 within the low-latency architectural context described in US10038481B2.

Motivation to Combine:
A PHOSITA, aiming to develop a highly efficient and low-latency FPGA system for applications like high-frequency trading, would be directly motivated to combine the teachings of these patents. US9602283B2 clearly states the technical problem of synchronizing clocks within an FPGA to minimize latency for such applications. US10038481B2 offers an FPGA architecture explicitly designed to achieve low latency by avoiding clock domain crossing operations. However, this architecture still requires a robust method for synchronizing the receiver and transmitter clocks to operate effectively without CDCs. US10547432B2 provides precisely this missing piece: an internal, active feedback loop for phase adjustment of clocks within an FPGA using a phase detector, an internal phase controller, and an adjustable PLL or oscillator.

The combination is driven by the clear objective of constructing a complete, high-performance FPGA system where the receiver and transmitter clocks are precisely phase-aligned through an internal feedback mechanism, thereby eliminating the need for latency-introducing CDC circuits and fulfilling the stated goals of low latency and effective time synchronization. The common inventorship and assignment across these patents further supports the notion that these concepts are synergistic and would naturally be combined by those working in the field.

Therefore, the independent claims of US11329655, describing an FPGA system and method for low-latency data processing with internal phase-locked loop-based clock synchronization, would have been obvious to a PHOSITA given the combined teachings of US9602283B2, US10038481B2, and US10547432B2. The general concepts of clock synchronization using phase detectors and adjustable oscillators, as further described in US8279930B2, would also reinforce this obviousness.