Prior art

To identify the most relevant prior art for US patent 11316014, I will use the patent's own citations from the Google Patents link provided. The "Citations (20)" and "Family Cites Families (67)" sections list the prior art considered by the examiner and other related patents. I will focus on the "Citations (20)" as these are the direct prior art references cited in the examination of US11316014.

Here's the analysis of the most relevant prior art for US Patent 11,316,014, focusing on the "Citations (20)" section from the provided patent text. These are the patents cited by the examiner during prosecution.

Most Relevant Prior Art for US Patent 11,316,014

1. US4160985A

• Full Citation: US4160985A, "Photosensing arrays with improved spatial resolution"
• Publication Date: July 10, 1979
• Brief Description: This patent describes photosensing arrays designed to improve spatial resolution. The context is related to imaging devices, which is one of the applications mentioned in US11316014 for graded dopant regions to enhance pixel and color resolution.
• Potentially Anticipates (35 U.S.C. § 102): Claims related to image sensors and improving pixel/color resolution. Specifically, it could potentially anticipate aspects of claim 19 which states, "The system of claim 1, wherein the at least one semiconductor device is an image sensor." and the broader concept of improving imaging ICs as discussed in the detailed description.

2. US4684971A

• Full Citation: US4684971A, "Ion implanted CMOS devices"
• Publication Date: August 4, 1987
• Brief Description: This patent describes CMOS devices fabricated using ion implantation. Ion implantation is a method for fabricating graded dopants mentioned in US11316014. The existence of ion-implanted CMOS devices is relevant to the manufacturing aspect.
• Potentially Anticipates (35 U.S.C. § 102): Claims related to CMOS devices and the fabrication method using ion implantation. Specifically, claim 7 states, "The system of claim 1, wherein the graded dopant is fabricated with an ion implantation process."

3. US4688063A

• Full Citation: US4688063A, "Dynamic ram cell with MOS trench capacitor in CMOS"
• Publication Date: August 18, 1987
• Brief Description: This patent describes a DRAM cell incorporating a MOS trench capacitor in a CMOS structure. DRAMs are explicitly mentioned in US11316014 as devices that can benefit from graded dopant regions (e.g., improving refresh time).
• Potentially Anticipates (35 U.S.C. § 102): Claims pertaining to DRAM devices. Specifically, claim 14 states, "The system of claim 1, wherein the at least one semiconductor device is a dynamic random access memory (DRAM)."

4. JPS6482563A

• Full Citation: JPS6482563A, "Semiconductor device"
• Publication Date: March 28, 1989
• Brief Description: While a detailed description requires translation, the title suggests a general semiconductor device. Given the broad applicability of graded dopants, this patent could be relevant to the general concept of semiconductor device structures.
• Potentially Anticipates (35 U.S.C. § 102): Without more specific details from the abstract or claims of JPS6482563A, it is difficult to pinpoint specific claims of US11316014. However, it could potentially anticipate broader aspects of semiconductor device design.

5. US4907058A

• Full Citation: US4907058A, "Complementary semiconductor device having a double well"
• Publication Date: March 6, 1990
• Brief Description: This patent describes a complementary semiconductor device with a double well structure. US11316014 discusses twin-well substrates in CMOS VLSI and the grading of n-well and p-well dopants.
• Potentially Anticipates (35 U.S.C. § 102): Claims relating to well regions and CMOS structures, such as claim 1, which mentions "at least one well region adjacent to the first or second active region containing at least one graded dopant region" and claim 5, "wherein the first active region and second active region of the at least one semiconductor device contain either p-channel or n-channel devices in n-wells or p-wells, respectively, and each well has at least one graded dopant."

6. US4994887A

• Full Citation: US4994887A, "High voltage merged bipolar/CMOS technology"
• Publication Date: February 19, 1991
• Brief Description: This patent describes a technology merging bipolar and CMOS devices, which relates to the broader field of integrated circuits that US11316014 aims to improve. IGBTs, which are a combination of MOSFET and BJT, are specifically mentioned in US11316014.
• Potentially Anticipates (35 U.S.C. § 102): Claims related to integrated circuits and combinations of different transistor types.

7. US5835402A

• Full Citation: US5835402A, "Non-volatile storage for standard CMOS integrated circuits"
• Publication Date: November 10, 1998
• Brief Description: This patent describes non-volatile storage for standard CMOS integrated circuits. US11316014 explicitly discusses improving nonvolatile memory like NAND flash by decreasing programming time.
• Potentially Anticipates (35 U.S.C. § 102): Claims related to flash memory and nonvolatile memory. Specifically, claim 16 states, "The system of claim 1, wherein the at least one semiconductor device is a flash memory."

8. US6025237A

• Full Citation: US6025237A, "Methods of forming field effect transistors having graded drain region doping profiles therein"
• Publication Date: February 15, 2000
• Brief Description: This patent directly discusses methods of forming FETs with graded drain region doping profiles. This is highly relevant as US11316014 claims graded dopant concentrations to aid carrier movement in active regions and discusses accelerating majority carriers towards the drain in MOS devices.
• Potentially Anticipates (35 U.S.C. § 102): Claims related to graded dopant concentrations in active regions and carrier movement, particularly in MOS devices. This could impact claims 1 and 21, as well as their dependent claims related to active regions and graded dopants.

9. US20010028097A1

• Full Citation: US20010028097A1, "Semiconductor device having buried-type element isolation structure and method of manufacturing the same"
• Publication Date: October 11, 2001
• Brief Description: This publication details a semiconductor device with a buried isolation structure. Isolation regions are mentioned in US11316014 as areas where dopant concentrations can be graded.
• Potentially Anticipates (35 U.S.C. § 102): Claims related to isolation regions. Specifically, claim 6 states, "The system of claim 1, wherein the first active region and second active region of the at least one semiconductor device are each separated by at least one isolation region."

10. US6384431B1

• Full Citation: US6384431B1, "Insulated gate bipolar transistor"
• Publication Date: May 7, 2002
• Brief Description: This patent describes an Insulated Gate Bipolar Transistor (IGBT). US11316014 heavily focuses on improving IGBTs through graded dopant regions, particularly in the epitaxial drift region.
• Potentially Anticipates (35 U.S.C. § 102): Claims related to IGBTs and their structure, especially with respect to the drift region. The detailed description of US11316014 elaborates significantly on the benefits of graded dopants in IGBTs.

11. US6465862B1

• Full Citation: US6465862B1, "Method and apparatus for implementing efficient CMOS photo sensors"
• Publication Date: October 15, 2002
• Brief Description: This patent describes efficient CMOS photo sensors. US11316014 specifically mentions enhancing pixel and color resolution in digital camera ICs and CMOS digital images.
• Potentially Anticipates (35 U.S.C. § 102): Claims related to image sensors and CMOS technology for imaging, impacting claim 19.

12. US20020195656A1

• Full Citation: US20020195656A1, "Semiconductor power device"
• Publication Date: December 26, 2002
• Brief Description: This publication describes a semiconductor power device. US11316014 applies to various power MOS transistors and IGBTs, which are power devices.
• Potentially Anticipates (35 U.S.C. § 102): Broad claims related to semiconductor power devices.

13. JP2003051551A

• Full Citation: JP2003051551A, "Semiconductor device manufacturing method and semiconductor device"
• Publication Date: February 21, 2003
• Brief Description: This Japanese patent application, while requiring translation for full details, concerns both a semiconductor device and its manufacturing method, making it broadly relevant to the subject matter of US11316014.
• Potentially Anticipates (35 U.S.C. § 102): General claims regarding semiconductor devices and their manufacturing, similar to JPS6482563A.

14. JP2003218356A

• Full Citation: JP2003218356A, "Manufacturing method and design method of SOI semiconductor device and SOI semiconductor device"
• Publication Date: July 31, 2003
• Brief Description: This Japanese patent application focuses on SOI (Silicon-on-Insulator) semiconductor devices and their manufacturing/design methods. While US11316014 focuses primarily on bulk silicon, the broad concepts of device manufacturing and design could overlap.
• Potentially Anticipates (35 U.S.C. § 102): General claims regarding semiconductor device manufacturing and design.

15. US20030183856A1

• Full Citation: US20030183856A1, "Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same"
• Publication Date: October 2, 2003
• Brief Description: This publication directly discusses a semiconductor device with a retrograde dopant profile in a channel region. Retrograde wells are explicitly mentioned in the background of US11316014, and the patent's invention aims to improve upon such techniques. The concept of a graded channel in JFETs is also mentioned in the detailed description.
• Potentially Anticipates (35 U.S.C. § 102): Claims relating to graded or retrograde dopant profiles in active regions and channels, potentially impacting claims 1, 5, and 21.

16. WO2004049453A1

• Full Citation: WO2004049453A1, "Retrograde channel doping to improve short channel effect"
• Publication Date: June 10, 2004
• Brief Description: This international publication describes retrograde channel doping to improve short channel effects. Similar to US20030183856A1, this is highly relevant to the concept of graded dopant profiles in active regions and channels.
• Potentially Anticipates (35 U.S.C. § 102): Claims relating to graded or retrograde dopant profiles in active regions and channels, potentially impacting claims 1, 5, and 21.

17. US20170243876A1

• Full Citation: US20170243876A1, "Semiconductor devices with graded dopant regions"
• Publication Date: August 24, 2017
• Brief Description: This is a later publication from Greenthread, LLC itself, and is part of the patent family (a continuation of the original application that led to US11316014). As such, it is not prior art to US11316014 but a related patent application. The priority date of US11316014 (September 3, 2004) predates this publication.
• Potentially Anticipates (35 U.S.C. § 102): Not applicable as this is a related, later publication and not prior art.

18. US20070045682A1

• Full Citation: US20070045682A1, "Imager with gradient doped EPI layer"
• Publication Date: March 1, 2007
• Brief Description: This publication describes an imager with a gradient-doped epitaxial (EPI) layer. The use of graded dopants in imaging ICs is a key aspect of US11316014. The priority date of US11316014 (September 3, 2004) predates this publication. However, it is cited as prior art, which implies an earlier effective filing date or invention date than its publication date. For the purposes of this analysis, assuming it's cited as prior art by the examiner, its content is relevant.
• Potentially Anticipates (35 U.S.C. § 102): Claims related to image sensors with graded dopant regions, especially in epitaxial layers, impacting claim 19 and the general discussion of imaging IC improvements.

19. US20080142899A1

• Full Citation: US20080142899A1, "Radiation immunity of integrated circuits using backside die contact and electrically conductive layers"
• Publication Date: June 19, 2008
• Brief Description: This publication discusses radiation immunity in integrated circuits. While US11316014 focuses on performance improvements through dopant grading, some applications like DRAM refresh time improvement could indirectly relate to mitigating effects of spurious carriers, which can be radiation-induced. However, it's not a direct match to graded dopants for carrier movement. The priority date of US11316014 (September 3, 2004) predates this publication.
• Potentially Anticipates (35 U.S.C. § 102): Less direct anticipation, possibly very broad concepts of integrated circuit improvement, but not specifically the graded dopant aspect for carrier movement as claimed.

20. US20140034997A1

• Full Citation: US20140034997A1, "Bipolar punch-through semiconductor device and method for manufacturing such a semiconductor device"
• Publication Date: February 6, 2014
• Brief Description: This publication describes a bipolar punch-through semiconductor device. US11316014 specifically mentions punch-through IGBTs and establishing a donor gradient in the emitter-drift epitaxial base region junction of such devices. The priority date of US11316014 (September 3, 2004) predates this publication.
• Potentially Anticipates (35 U.S.C. § 102): Claims related to punch-through IGBTs and graded dopant regions within them, as extensively discussed in the detailed description of US11316014.