Obviousness

Obviousness Analysis of U.S. Patent 11,316,014 under 35 U.S.C. § 103

The independent claims of U.S. Patent 11,316,014, which broadly cover electronic systems with semiconductor devices incorporating graded dopant regions to aid carrier movement, would likely be rendered obvious under 35 U.S.C. § 103 by combining existing prior art references. The core inventive concept—using graded dopant concentrations to control charge carrier movement for performance improvement in various semiconductor devices—represents a logical extension of well-established principles in semiconductor physics and manufacturing, particularly when addressing known problems in the field.

A person having ordinary skill in the art (PHOSITA) at the time of the invention (priority date September 3, 2004) would have been motivated to combine several prior art teachings to arrive at the claimed invention, with predictable results.

Key Elements of the Independent Claims (1 and 21) and Corresponding Prior Art

The independent claims describe an electronic system comprising a semiconductor device with:

• A substrate having a surface.
• First and second active regions adjacent the surface, of an opposite doping type to the substrate, within which transistors (e.g., digital logic, p-channel, n-channel, CMOS) are formed.
• At least a portion of at least one of these active regions or an adjacent well region having at least one graded dopant concentration.
• This graded dopant concentration is configured to aid carrier movement from the active regions/surface towards an area of the substrate where there are no active regions.
• Claim 21 further specifies the gradient types (linear, quasilinear, error function, complementary error function).

Combinations of Prior Art References and Motivations for Combination

1. Obviousness of Graded Dopants in Active Regions/Channels of MOS/CMOS Devices for Performance Enhancement:

• Prior Art:
  • US20030183856A1 (Wieczorek) explicitly teaches a "semiconductor device having a retrograde dopant profile in a channel region" and a method for fabricating it. Retrograde doping is a form of graded doping.
  • WO2004049453A1 (Advanced Micro Devices, Inc.) similarly teaches "retrograde channel doping to improve short channel effect."
  • US6025237A (Fairchild Korea Semiconductor, Ltd.) discloses "methods of forming field effect transistors having graded drain region doping profiles therein."
  • US4684971A (American Telephone And Telegraph Company) describes "ion implanted CMOS devices," establishing the foundational technology of CMOS.
  • US4907058A (Hitachi, Ltd.) shows a "complementary semiconductor device having a double well," further detailing CMOS structures.
• Motivation for Combination: A PHOSITA would have been motivated to apply known graded dopant profiles, as taught by Wieczorek, Advanced Micro Devices, and Fairchild, to the channel or drain regions of CMOS transistors (structures known from AT&T and Hitachi). The motivation would be to improve device performance characteristics such as short channel effects or current characteristics by precisely controlling carrier movement. The background of US11316014 itself notes that "Most MOS devices use a uniformly doped substrate (or a well region)," implicitly recognizing the potential for improvement through non-uniform doping in these areas.

2. Obviousness of Graded Dopants in Well Regions for Minority Carrier Management in Memory and Imaging Applications:

• Prior Art:
  • US6310366B1 (Micron Technology, Inc.) describes a "retrograde well structure for a CMOS imager" specifically to reduce dark current and improve light sensitivity. Retrograde wells are a direct example of graded dopant regions in wells.
  • US4481522A (Rca Corporation) teaches "CCD Imagers with substrates having drift field." A drift field is typically created by a dopant gradient to aid carrier movement (sweeping them away) for improved imaging performance.
  • US6472715B1 (Lsi Logic Corporation) details a "Reduced soft error rate (SER) construction for integrated circuit structures," a problem often caused by spurious minority carriers in memory, which US11316014 also aims to mitigate.
  • US6621064B2 (Texas Instruments Incorporated) discloses a "CMOS photodiode having reduced dark current and improved light sensitivity and responsivity," indicating dopant engineering for imaging performance.
  • US4688063A (International Business Machines Corporation) teaches "Dynamic ram cell with MOS trench capacitor in CMOS," establishing the context of DRAM technology.
• Motivation for Combination: A PHOSITA, aware of the performance limitations caused by minority carriers in CMOS imagers (e.g., dark current, as addressed by Micron and Texas Instruments) and DRAMs (e.g., soft error rate, as addressed by LSI Logic, and refresh time degradation, as mentioned in US11316014's background), would be highly motivated to combine the known concept of a retrograde well (Micron) or drift fields (RCA) with the general understanding of dopant gradients to create graded dopant regions within or adjacent to wells. This combination would predictably improve device performance by sweeping unwanted minority carriers away from active regions (as explicitly discussed in US11316014's background regarding retrograde and halo wells).

3. Obviousness of Generalizing Graded Doping for Carrier Acceleration in Various Semiconductor Devices:

• Prior Art:
  • US5448087A (Trw Inc.) and US5329144A (At&T Bell Laboratories) both explicitly teach "graded base doping" or "graded base structure" in Heterojunction Bipolar Transistors (HBTs). US11316014's background acknowledges that efforts have been made in "graded base transistors to create an aiding drift field to enhance the diffusing minority carrier's speed from emitter to collector."
  • US4001864A (Gibbons James F), though for solar cells, demonstrates the fundamental principle of using "graded impurity concentration to enhance efficiency" by aiding carrier movement.
  • WO2003025984A2 (Amberwave Systems Corporation) broadly describes "semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same," demonstrating general knowledge of using impurity gradients.
  • DE10131704A1 (Atmel Germany Gmbh) explicitly describes a "Method for doping a semiconductor body."
• Motivation for Combination: Given the established benefits of graded doping in specific devices like BJTs (TRW, AT&T) and solar cells (Gibbons) for accelerating carriers and improving performance, a PHOSITA would be motivated to extend these known principles to other semiconductor devices. This includes, for example, applying graded dopants to power MOS transistors and IGBTs (devices mentioned in US11316014 as areas of application, with Denso's US6384431B1 describing an IGBT). The motivation would be to achieve similar, predictable improvements in carrier movement, such as increased frequency, faster switching, or reduced recombination, by creating an internal drift field through the graded dopant. The choice of specific gradient types (linear, quasi-linear, error function, complementary error function), as enumerated in Claim 21, are conventional mathematical profiles for tailoring dopant concentrations and achieving desired electric field characteristics, as generally suggested by Amberwave's "defined impurity gradients".

Conclusion

The claims of US11316014 represent an obvious combination of existing semiconductor device structures with known techniques for dopant grading to control carrier movement. The problems addressed by the patent, such as improving frequency, refresh time, or image quality by managing minority or majority carriers, were well-recognized in the prior art. Consequently, a PHOSITA would have been motivated to apply these known graded doping techniques to the relevant regions of various semiconductor devices to achieve predictable performance benefits, rendering the claimed invention obvious.